ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks

An increasing number of multi-deck cells occupying multiple rows (e.g. multi-bit registers) are used in advanced node technologies to achieve low power and high performance. The multi-deck standard cell legalization not only should remove all overlaps between cells but also should satisfy delicate and complicated design rules with preserving the quality of the given placement by applying the minimal perturbation. In addition, the process must be fast and robust to handle the sheer number of cells in the state-of-the-art designs. For this purpose, we have defined an evaluation metric based on maximum, average cell movements, and Half Perimeter Wire Length (HPWL) as well as runtime of the legalization algorithm. In addition, we have introduced a set of benchmarks that include multi-deck cells with a range of heights (1–4 row heights).

[1]  Wai-Kei Mak,et al.  Mixed-Cell-Height Standard Cell Placement Legalization , 2017, ACM Great Lakes Symposium on VLSI.

[2]  Andrew A. Kennings,et al.  Detailed placement accounting for technology constraints , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[3]  Minsik Cho,et al.  History-based VLSI legalization using network flow , 2010, Design Automation Conference.

[4]  D. Chinnery,et al.  ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement , 2015, ISPD.

[5]  Evangeline F. Y. Young,et al.  Cell density-driven detailed placement with displacement constraint , 2014, ISPD '14.

[6]  Ulf Schlichtmann,et al.  Abacus: fast legalization of standard cell circuits with minimal movement , 2008, ISPD '08.

[7]  Ismail Bustany,et al.  ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement , 2014, ISPD '14.

[8]  David Z. Pan,et al.  MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Ulrich Brenner.  BonnPlace Legalization: Minimizing Movement by Iterative Augmentation , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Ismail Bustany,et al.  NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  David T. Westwick,et al.  High performance global placement and legalization accounting for fence regions , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Ismail Bustany,et al.  A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement , 2017, ISPD.

[13]  David T. Westwick,et al.  Eh?Placer , 2016, ACM Trans. Design Autom. Electr. Syst..

[14]  Evangeline F. Y. Young,et al.  Legalization algorithm for multiple-row height standard cell design , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Chris C. N. Chu,et al.  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control , 2007, 2007 Asia and South Pacific Design Automation Conference.

[16]  David Z. Pan,et al.  Diffusion-based placement migration , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[17]  David K. Smith.  Network Flows: Theory, Algorithms, and Applications , 1994 .

[18]  Yao-Wen Chang,et al.  Toward optimal legalization for mixed-cell-height circuit designs , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).