Rounded edge mesa for submicron SOI CMOS process

Different isolation features have been proposed for SOI: LOCOS, mesa, reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. We present here the Rounded Edge Mesa (REM) which allows an accurate control of the gate dimensions without residues. Characteristics of devices fabricated with 0.7 μm SOI CMOS process are presented.