New methodology for thermal analysis of multi-core processors based on dedicated ASIC

Abstract Accurate prediction of thermal phenomena occurring in multi-core processors manufactured in new technologies prove to be both crucial and challenging. Therefore, in this paper, we introduce a new methodology for thermal analysis of such chips. The novelty of our approach is the use of a dedicated ASIC ( Application-Specific Integrated Circuit ), composed of a 16×24 array of heat cells, which emulates the power dissipation in a real processor and allows observing the chip temperature distribution in real-time. The ASIC takes as an input the power trace computed by the execution of benchmarks on a cycle-accurate processor simulator. The entire methodology flow is thoroughly described in the paper, including the details about the chip design and power modeling techniques. Post-layout simulations of our ASIC are used to verify the correctness of the design, whereas our approach to power modeling is validated using preliminary thermal simulations performed with existing software tools.

[1]  E. W. Williams,et al.  Integrated converters : D to A and D architectures, analysis and simulation , 2001 .

[2]  Richard E. Kessler,et al.  The Alpha 21264 microprocessor architecture , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[3]  Glenn Reinman,et al.  Low-Overhead Core Swapping for Thermal Management , 2004, PACS.

[4]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[5]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  A Louri,et al.  Hot spots and core-to-core thermal coupling in future multi-core architectures , 2010, 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[7]  Seda Ogrenci Memik,et al.  Systematic temperature sensor allocation and placement for microprocessors , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[8]  Willy Sansen,et al.  analog design essentials , 2011 .

[9]  Lian-Tuu Yeh,et al.  Thermal Management of Microelectronic Equipment , 2002 .

[10]  Kevin Skadron,et al.  Many-core design from a thermal perspective , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[11]  M. Szermer,et al.  Cache leakage power estimation using architectural model for 32 nm and 16 nm technology nodes , 2012, 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[12]  M. Szermer,et al.  Test ASIC for investigation of thermal coupling in Many-Core Architectures , 2012, 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[13]  Krste Asanovic,et al.  Reducing power density through activity migration , 2003, ISLPED '03.

[14]  Dean M. Tullsen,et al.  Reducing power with dynamic critical path information , 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

[15]  Kevin Skadron,et al.  Hot Leakage: An Architectural, Temperature-Aware Model of Subthreshold and Gate Leakage , 2012 .

[16]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[17]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[18]  Kevin Skadron,et al.  Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[19]  Shekhar Y. Borkar,et al.  Thousand Core ChipsA Technology Perspective , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[20]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[21]  Coniferous softwood.  GENERAL TERMS , 2003 .

[22]  Gurindar S. Sohi,et al.  A static power model for architects , 2000, MICRO 33.

[23]  Z. Kulesza,et al.  Automated stand for thermal characterization of electronic packages , 2011, 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[24]  Dean M. Tullsen,et al.  Reducing power with dynamic critical path information , 2001, MICRO.