A workload generation environment for trace-driven simulation of shared-bus multiprocessors
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Luigi M. Ricciardi | Cosimo Antonio Prete | Roberto Giorgi | Gianpaolo Prina | C. Prete | L. Ricciardi | R. Giorgi | G. Prina
[1] A. Gupta,et al. Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results , 1989, ISCA '89.
[2] W. Kent Fuchs,et al. Address tracing of parallel systems via TRAPEDS , 1992, Microprocess. Microsystems.
[3] Alan Jay Smith,et al. Evaluation of cache consistency algorithm performance , 1996, Proceedings of MASCOTS '96 - 4th International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.
[4] Susan J. Eggers,et al. Techniques for efficient inline tracing on a shared-memory multiprocessor , 1990, SIGMETRICS '90.
[5] Mark S. Squillante,et al. Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling , 1993, IEEE Trans. Parallel Distributed Syst..
[6] Peter S. Magnusson,et al. Efficient memory simulation in SimICS , 1995, Proceedings of Simulation Symposium.
[7] Mary K. Vernon,et al. An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols , 1988, ISCA '88.
[8] Veljko Milutinovic,et al. The Cache Coherence Problem in Shared-Memory Multiprocessors: Software Solutions , 1996 .
[9] Randy H. Katz,et al. Evaluating The Performance Of Four Snooping Cache Coherency Protocols , 1989, The 16th Annual International Symposium on Computer Architecture.
[10] Anoop Gupta,et al. Complete computer system simulation: the SimOS approach , 1995, IEEE Parallel Distributed Technol. Syst. Appl..
[11] Anna R. Karlin,et al. Competitive snoopy caching , 1986, 27th Annual Symposium on Foundations of Computer Science (sfcs 1986).
[12] Anoop Gupta,et al. Architectural and implementation tradeoffs in the design of multiple-context processors , 1992, ISCA.
[13] Randy H. Katz,et al. Simulation analysis of data-sharing in shared memory multiprocessors , 1989 .
[14] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[15] Luigi M. Ricciardi,et al. A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems , 1995, IEEE Trans. Parallel Distributed Syst..
[16] W. Kent Fuchs,et al. Address tracing for parallel machines , 1991, Computer.
[17] Randy H. Katz,et al. Implementing a cache consistency protocol , 1985, ISCA '85.
[18] Anoop Gupta,et al. Exploring The Benefits Of Multiple Hardware Contexts In A Multiprocessor Architecture: Preliminary Results , 1989, The 16th Annual International Symposium on Computer Architecture.
[19] Bart C. Vashaw. Address trace collection and trace driven simulation of bus based, shared memory multiprocessors , 1992 .
[20] Luigi M. Ricciardi,et al. A Selective Invalidation Strategy for Cache Coherence , 1995, IEICE Trans. Inf. Syst..
[21] Anant Agarwal,et al. APRIL: a processor architecture for multiprocessing , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[22] Kai Hwang,et al. Advanced computer architecture - parallelism, scalability, programmability , 1992 .
[23] Robert J. Fowler,et al. MINT: a front end for efficient simulation of shared-memory multiprocessors , 1994, Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.
[24] Carla Schlatter Ellis,et al. Accuracy of Memory Reference Traces of Parallel Computations in Trace-Driven Simulation , 1992, IEEE Trans. Parallel Distributed Syst..
[25] Anant Agarwal,et al. Multiprocessor cache analysis using ATUM , 1988, ISCA '88.
[26] J. Laudon,et al. Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.
[27] David E. Culler,et al. Analysis of multithreaded architectures for parallel computing , 1990, SPAA '90.
[28] David A. Patterson,et al. Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .
[29] Daniel E. Lenoski,et al. Scalable Shared-Memory Multiprocessing , 1995 .