An efficient design of reversible ternary full-adder/full-subtractor with low quantum cost

One of the major challenges of VLSI circuits is heat caused by energy loss. One of the successful solutions to this challenge is to design circuits in a reversible manner. Hence, the design of reversible circuits has attracted the attention of many researchers in the fields of low-power circuits design, DNA computing and quantum computing. Due to the benefits of ternary logic over binary logic such as reducing the complexity of interconnecting circuits, decreasing the occupied surface and reducing the number of quantum cells in quantum circuits, the ternary logic has been proposed for the design of VLSI circuits. In this paper, we first propose a new reversible ternary full-adder, called comprehensive reversible ternary full-adder, using the ternary logic capabilities. In the following, an efficient reversible ternary full-subtractor is provided. Finally, using the two proposed circuits, a new reversible ternary full-adder/full-subtractor is introduced. The results of the comparisons show that the proposed circuits have lower quantum cost and are more efficient than the other previous circuits.

[1]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[2]  Ashis Kumer Biswas,et al.  Efficient approaches for designing reversible Binary Coded Decimal adders , 2008, Microelectron. J..

[3]  J. C. Retamal,et al.  Qutrit quantum computer with trapped ions , 2003 .

[4]  Anas N. Al-Rabadi,et al.  A General Decomposition for Reversible Logic , 2001 .

[5]  Muhammad Mahbubur Rahman,et al.  Synthesis of Fault Tolerant Reversible Logic Circuits , 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.

[6]  H.T. Mouftah,et al.  A CMOS ternary ROM chip , 1988, [1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic.

[7]  Gerhard W. Dueck,et al.  A synthesis method for MVL reversible logic [multiple value logic] , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

[8]  Jr.,et al.  Multivalued logic gates for quantum computation , 2000, quant-ph/0002033.

[9]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[10]  J. Twamley,et al.  Trapped-ion qutrit spin molecule quantum computer , 2005 .

[11]  Mozammel H. A. Khan,et al.  Synthesis of quaternary reversible/quantum comparators , 2008, J. Syst. Archit..

[12]  Majid Mohammadi,et al.  Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares , 2013, Integr..

[13]  Mozammel H. A. Khan.  Design of ternary reversible sequential circuits , 2014, 8th International Conference on Electrical and Computer Engineering.

[14]  Jacqueline E. Rice,et al.  Synthesis of reversible logic functions using ternary Max-Min algebra , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[15]  M. Eshghi,et al.  On design of multiple-valued sequential reversible circuits for nanotechnology based systems , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[16]  Hafiz Md. Hasan Babu,et al.  Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing , 2015, 2015 IEEE International Symposium on Multiple-Valued Logic.

[17]  Robert Wille,et al.  Towards quantum reversible ternary coded decimal adder , 2017, Quantum Inf. Process..

[18]  Susmita Sur-Kolay,et al.  Synthesis Techniques for Ternary Quantum Logic , 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

[19]  George Epstein,et al.  The development of multiple-valued logic as related to computer science , 1974, Computer.

[20]  Majid Haghparast,et al.  Designing new ternary reversible subtractor circuits , 2017, Microprocess. Microsystems.

[21]  Hafiz Md. Hasan Babu,et al.  Design of a compact reversible fault tolerant division circuit , 2016, Microelectron. J..

[22]  Mozammel H. A. Khan,et al.  A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry , 2008, J. Syst. Archit..

[23]  Mark Glusker,et al.  The ternary calculating machine of Thomas Fowler , 2005 .

[24]  Mozammel H. A. Khan.  Design of Reversible/Quantum Ternary Multiplexer and Demultiplexer , 2006, Eng. Lett..

[25]  Majid Haghparast,et al.  Design of novel quantum/reversible ternary adder circuits , 2017 .

[26]  Mozammel H. A. Khan,et al.  Quantum ternary parallel adder/subtractor with partially-look-ahead carry , 2007, J. Syst. Archit..

[27]  Vitaly G. Deibuk,et al.  Design of a Ternary Reversible/Quantum Adder using Genetic Algorithm , 2015 .