Serial code accelerators for heterogeneous multi-core processor with 3D stacked memory

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[1]  Payman Zarkesh-Ha,et al.  Impact of three-dimensional architectures on interconnects in gigascale integration , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[3]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[4]  Narayanan Vijaykrishnan,et al.  Three-dimensional cache design exploration using 3DCacti , 2005, 2005 International Conference on Computer Design.

[5]  Thomas Brunschwiler,et al.  Thermal Management of Vertically Integrated Packages , 2008 .

[6]  A. Bellaouar,et al.  3.3-V BiCMOS current mode logic circuits for high-speed adders , 1993, 1993 Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[7]  T. Kenny,et al.  Closed-loop electroosmotic microchannel cooling system for VLSI circuits , 2002 .

[8]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[9]  John F. McDonald,et al.  High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic , 1991 .

[10]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[11]  Aamir Zia,et al.  Predicting the performance of a 3D processor-memory chip stack , 2005, IEEE Design & Test of Computers.

[12]  Manoj Sachdev,et al.  Thermal and Power Management of Integrated Circuits , 2006, Series on Integrated Circuits and Systems.

[13]  Kunle Olukotun,et al.  Niagara: a 32-way multithreaded Sparc processor , 2005, IEEE Micro.

[14]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[15]  James D. Meindl,et al.  A stochastic wire length distribution for gigascale integration (GSI) , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[16]  A.Y. Zeng,et al.  Wafer-level 3D manufacturing issues for streaming video processors , 2004, 2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530).

[17]  Antonio Rubio,et al.  Thermal testing of integrated circuits , 2002 .

[18]  Lutz J. Micheel.  Heterojunction bipolar technology for emitter-coupled multiple-valued logic in gigahertz adders and multipliers , 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

[19]  R. Pease,et al.  High-performance heat sinking for VLSI , 1981, IEEE Electron Device Letters.

[20]  M. Suzuoki,et al.  Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor , 2006, IEEE Journal of Solid-State Circuits.

[21]  Massimo Alioto,et al.  Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits , 1991 .

[22]  Xiaotong Zhuang,et al.  Reducing Cache Pollution via Dynamic Data Prefetch Filtering , 2007, IEEE Transactions on Computers.

[23]  Russell P. Kraft,et al.  SiGe HBT Microprocessor Core Test Vehicle , 2005, Proceedings of the IEEE.

[24]  David R. Greenberg,et al.  Scaling of SiGe Heterojunction Bipolar Transistors , 2005, Proceedings of the IEEE.

[25]  Xiaofeng Gao,et al.  Performance Sensitivity Studies for Strategic Applications , 2005, 2005 Users Group Conference (DOD-UGC'05).

[26]  C.K. Chen,et al.  A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.

[27]  Peter Ramm,et al.  3D Integration: Technology and Applications , 2008 .

[28]  Martin Burtscher,et al.  Bridging the processor-memory performance gap with 3D IC technology , 2005, IEEE Design & Test of Computers.

[29]  D. Tang,et al.  Bipolar circuit scaling , 1979, 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[30]  G. Amdhal,et al.  Validity of the single processor approach to achieving large scale computing capabilities , 1967, AFIPS '67 (Spring).

[31]  Christopher Blauth,et al.  Data, data, data… , 2007, International journal of clinical practice.

[32]  Bernard S. Meyerson,et al.  The early history of IBM's SiGe mixed signal technology , 2001 .

[33]  J. Cressler.  SiGe HBT technology: a new contender for Si-based RF and microwave circuit applications , 1998 .

[34]  Hsien-Hsin S. Lee,et al.  Thermal-aware 3D Microarchitectural Floorplanning , 2004 .

[35]  K.C. Saraswat,et al.  Thermal analysis of heterogeneous 3D ICs with various integration scenarios , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[36]  V. Moldenhauer,et al.  A 533-MHz BiCMOS superscalar RISC microprocessor , 1997 .

[37]  John F. McDonald,et al.  Three dimensional stacking with diamond sheet heat extraction for subnanosecond machine design , 1995, Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI).

[38]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[39]  J.F. McDonald,et al.  A 0.29 ns 32-word by 32 b three-port bipolar register file implemented using a SiGe HBT BiCMOS technology , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[40]  Gabriel H. Loh,et al.  Thermal analysis of a 3D die-stacked high-performance microprocessor , 2006, GLSVLSI '06.

[41]  Yuan Xie,et al.  Design space exploration for 3D architectures , 2006, JETC.

[42]  G. Q. Zhang,et al.  Benefiting from Thermal and Mechanical Simulation in Micro-Electronics , 2010 .

[43]  Bernard S. Meyerson,et al.  113-GHz fT graded-base SiGe HBTs , 1993, 51st Annual Device Research Conference.

[44]  Donald Yeung,et al.  BioBench: A Benchmark Suite of Bioinformatics Applications , 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

[45]  Jack Dongarra,et al.  MPI: The Complete Reference , 1996 .

[46]  Ricardo Fernández,et al.  RSIM x 86 : A COST-EFFECTIVE PERFORMANCE SIMULATOR , 2005 .

[47]  Lei Jiang,et al.  Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[48]  Christopher J. Hughes,et al.  RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors , 2002, Computer.

[49]  Krisztián Flautner,et al.  PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor , 2006, ASPLOS XII.

[50]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[51]  Kaustav Banerjee,et al.  A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[52]  A. Nahman,et al.  Wire-length distribution of three-dimensional integrated circuits , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[53]  李幼升,et al.  Ph , 1989 .

[54]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[55]  Kia Bazargan,et al.  Placement and routing in 3D integrated circuits , 2005, IEEE Design & Test of Computers.

[56]  S. Jeng,et al.  SiGe HBTs with cut-off frequency of 350 GHz , 2002, Digest. International Electron Devices Meeting,.

[57]  Michael Sung,et al.  Semiconductor on diamond (SOD) for system on chip (SoC) architectures , 2006 .

[58]  W. Robert Daasch,et al.  A thermal-aware superscalar microprocessor , 2002, Proceedings International Symposium on Quality Electronic Design.

[59]  Mani Azimi,et al.  Integration Challenges and Tradeoffs for Terascale Architectures , 2007 .

[60]  Philip Garrou,et al.  Future ICs go vertical , 2005 .

[61]  T. Wada,et al.  An analytical access time model for on-chip cache memories , 1992 .

[62]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[63]  Massimo Alioto,et al.  CML and ECL: optimized design and comparison , 1999 .

[64]  James S. Dunn,et al.  Status and Direction of Communication Technologies - SiGe BiCMOS and RFCMOS , 2005, Proceedings of the IEEE.