An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices

In this paper, a new RNS architecture to compute the 1-D DWT is introduced. It makes use of the relation between the coefficients of the low-pass and high-pass decomposition filters for orthogonal wavelet families to compute the transform with a minimum number of modular multipliers. These multipliers are based on pipelined LUTs (Look-Up Tables) and are used in consecutive cycles by each filter. Two modular adder trees operating at half of the sampling rate and controlled by out-of-phase clocks compute the approximation and detail sequences. A 6-tap Daubechies analysis filter bank was synthesized at structural level using VHDL. Altera FLEX10K FPL devices were considered to map binary 2's complement arithmetic and RNS solutions and to conduct performance simulations. Thus, a significant throughput improvement of up to 75% is achieved for the proposed RNS architecture using up to 8-bit length modulus set. It is shown that the selection of three 7-bit channels is optimum for an FPL implementation while four 6-bit RNS channels would be the best choice for a VLSI architecture in order to reduce chip area.