LDPC decoder architectures

This chapter discusses various approaches for practical implementation of low density parity check (LDPC) decoders. Firstly, a fully parallel architecture is described and then a serial architecture is presented. A partially-parallel architecture, which comprises properties of both parallel and serial architectures, is also discussed. Each of the above architectures has its own merits and demerits. Selection of different hardware architectures does not affect the error correction performance of an LDPC code or decoding algorithm, because key parameters such as the code length, code rate, and structure of the parity check matrix can remain same irrespective of the hardware architecture. However, the hardware architecture has significant impact on the decoding throughput, logic and memory requirements, and power consumption. The complexity of hardware implementation of a decoder also depends on the decoding algorithm and the structure of the parity check matrix. Therefore, it is important to choose an appropriate architecture based on the application and product requirements.

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