LDPC decoder architectures
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[1] Jing Wang,et al. Modified min-sum decoding algorithm for LDPC codes based on classified correction , 2008, 2008 Third International Conference on Communications and Networking in China.
[2] Shie Mannor,et al. Fully Parallel Stochastic LDPC Decoders , 2008, IEEE Transactions on Signal Processing.
[3] W.J. Gross,et al. Stochastic Implementation of LDPC Decoders , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..
[4] Joseph R. Cavallaro,et al. Semi-parallel reconfigurable architectures for real-time LDPC decoding , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..
[5] Euncheol Kim,et al. Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.
[6] Chang-Soo Park,et al. A novel partially parallel architecture for high-throughput LDPC Decoder for DVB-S2 , 2010, IEEE Transactions on Consumer Electronics.
[7] Hans-Jörg Pfleiderer,et al. FPGA implementation of a flexible decoder for long LDPC codes , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[8] Paul Fortier,et al. FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[9] Wang Ling Goh,et al. A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes , 2008, 2008 2nd International Conference on Signals, Circuits and Systems.
[10] Vikram Arkalgud Chandrasetty,et al. A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders , 2011, 2011 IEEE International Conference on Multimedia and Expo.
[11] Hong Ding,et al. Design and Implementation for High Speed LDPC Decoder with Layered Decoding , 2009, 2009 WRI International Conference on Communications and Mobile Computing.
[12] Ning Chen,et al. Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[13] Stephen G. Wilson,et al. Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design , 2007, IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference.
[14] Shie Mannor,et al. An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding , 2007, 2007 IEEE Workshop on Signal Processing Systems.
[15] Zhongfeng Wang,et al. A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[16] Yi-Hsing Chien,et al. A High Throughput H-QC LDPC Decoder , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[17] Tao Xiaofeng,et al. A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder , 2008, VTC Spring 2008 - IEEE Vehicular Technology Conference.
[18] Nozomu Togawa,et al. Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm , 2005, 2005 International Conference on Computer Design.
[19] Ali Emre Pusane,et al. A low-cost serial decoder architecture for low-density parity-check convolutional codes , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[21] Keshab K. Parhi,et al. A 54 Mbps (3,6)-regular FPGA LDPC decoder , 2002, IEEE Workshop on Signal Processing Systems.
[22] Zhixing Yang,et al. High-throughput LDPC decoding architecture , 2008, 2008 International Conference on Communications, Circuits and Systems.
[23] Paul Saunders,et al. A Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC codes , 2006 .
[24] D.A. Morero,et al. Parallel architecture for decoding LDPC Codes on high speed communication systems , 2008, 2008 Argentine School of Micro-Nanoelectronics, Technology and Applications.
[25] Lei Yang,et al. An FPGA implementation of low-density parity-check code decoder with multi-rate capability , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[26] Zhaoyang Zhang,et al. Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder , 2007, 2007 Second International Conference on Communications and Networking in China.
[27] Samuel Dolinar,et al. A scalable architecture of a structured LDPC decoder , 2004, International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings..
[28] Vikram Arkalgud Chandrasetty,et al. An area efficient LDPC decoder using a reduced complexity min-sum algorithm , 2012, Integr..
[29] James A. Ritcey,et al. Finite precision implementation of LDPC coded M-ary modulation over wireless channels , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.
[30] Frank R. Kschischang,et al. A bit-serial approximate min-sum LDPC decoder and FPGA implementation , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[31] A. Banihashemi,et al. FPGA implementation of variants of min-sum algorithm , 2008, 2008 24th Biennial Symposium on Communications.
[32] François Charot,et al. A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture , 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.