Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip

Abstract This paper presents a technique using a genetic algorithm to compute an efficient routing for an application-specific NoC (Network-on-Chip). The main goal of this paper is to introduce multi-objective optimization techniques to address the NoC routing. Thus, Pareto optimization has been used to determine non-dominated solutions according to two fixed objectives: (i) avoiding the reuse of same links as far as possible to reduce congestion; (ii) reducing the number of loops to limit the risk of deadlocks. The proposed method called MORGA (Multi-Objective Routing based on Genetic Algorithm) uses two steps: (i) an off-line process consisting at selecting a non-dominated solution among a pre-calculated population of solutions; (ii) an on-line process allowing the data transmission based on the built solution by the use of routing tables. MORGA is also applicable in the presence of permanent faulty links by calculating fault-free solutions. A reconfiguration of routing tables is performed when a new application is loaded on the system. Results show how a selection of the most appropriate solution can provide considerable improvement in performance.

[1]  Masoud Dehyadegari,et al.  Power and delay optimization for network on chip , 2005, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005..

[2]  An-Yeu Wu,et al.  Regional ACO-based routing for load-balancing in NoC systems , 2010, 2010 Second World Congress on Nature and Biologically Inspired Computing (NaBIC).

[3]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[4]  Xiaola Lin,et al.  The Repetitive Turn Model for Adaptive Routing , 2017, IEEE Transactions on Computers.

[5]  J. Sebastian,et al.  The Pure Zigzag Model for routing in a NoC , 2012, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET).

[6]  Colin Reeves.  Genetic Algorithms , 2003, Handbook of Metaheuristics.

[7]  J. Y. Yen.  Finding the K Shortest Loopless Paths in a Network , 1971 .

[8]  Pasi Liljeberg,et al.  Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs , 2014, Microprocess. Microsystems.

[9]  Wu,et al.  Genetic Algorithm Based Mapping and Routing Approach for Network on Chip Architectures , 2010 .

[10]  G. Edward Suh,et al.  Application-aware deadlock-free oblivious routing , 2009, ISCA '09.

[11]  H. Jonathan Chao,et al.  HOPE: Hotspot congestion control for Clos network on chip , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[12]  Zahra Shirmohammadi,et al.  LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Pasi Liljeberg,et al.  Adaptive reinforcement learning method for networks-on-chip , 2012, 2012 International Conference on Embedded Computer Systems (SAMOS).

[14]  An-Yeu Wu,et al.  ACO-based fault-aware routing algorithm for Network-on-Chip systems , 2013, SiPS 2013 Proceedings.

[15]  An-Yeu Wu,et al.  Implementation of ACO-Based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems , 2013, IEEE Embedded Systems Letters.

[16]  Mouloud Koudil,et al.  NoC routing protocols - objective-based classification , 2016, J. Syst. Archit..

[17]  Li Wang,et al.  NoC power optimization using combined routing algorithms , 2017, 2017 IEEE/ACIS 16th International Conference on Computer and Information Science (ICIS).

[18]  Masoud Daneshtalab,et al.  NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[19]  En-Jui Chang,et al.  ACO-based Cascaded Adaptive Routing for traffic balancing in NoC systems , 2010, The 2010 International Conference on Green Circuits and Systems.

[20]  Juan M. Orduña,et al.  A multi-objective strategy for concurrent mapping and routing in networks on chip , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

[21]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[22]  En-Jui Chang,et al.  Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems , 2017, IEEE Transactions on Parallel and Distributed Systems.

[23]  Dongkun Shin,et al.  Power-aware communication optimization for networks-on-chips with voltage scalable links , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[24]  Mahdi Nikdast,et al.  An Innovational Intermittent Algorithm in Networks-On-Chip (NOC) , 2008 .

[25]  DaeHo Seo,et al.  Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks , 2005, ISCA 2005.

[26]  Takahiro Watanabe,et al.  High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC , 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

[27]  E. Cantu-Paz,et al.  The Gambler's Ruin Problem, Genetic Algorithms, and the Sizing of Populations , 1997, Evolutionary Computation.

[28]  Massoud Pedram,et al.  A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution , 2009, J. Low Power Electron..

[29]  Hafizur Rahaman,et al.  Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach , 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

[30]  Srinivasan Seshan,et al.  On-chip networks from a networking perspective: congestion and scalability in many-core interconnects , 2012, SIGCOMM '12.

[31]  N. Nedjah,et al.  ACO approach in static routing for network-on-chips with 3D mesh topology , 2013, 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS).

[32]  Hannu Tenhunen,et al.  HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[33]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1998, ISCA '98.

[34]  An-Yeu Wu,et al.  ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems , 2012, 2012 IEEE Workshop on Signal Processing Systems.

[35]  Marc Sevaux,et al.  Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations , 2013, 2013 Euromicro Conference on Digital System Design.

[36]  Nooshin Nosrati,et al.  G-CARA: A Global Congestion-Aware Routing Algorithm for traffic management in 3D networks-on-chip , 2017, 2017 Iranian Conference on Electrical Engineering (ICEE).

[37]  Jie Wu,et al.  A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.

[38]  Vincenzo Catania,et al.  Application Specific Routing Algorithms for Networks on Chip , 2009, IEEE Transactions on Parallel and Distributed Systems.