Efficient fault tolerant cache memory design

Abstract In this paper we firstly discuss the consequences of cache memory defects/faults in the operation of the system and we show that cache tag defects/faults compared to cache data defects/faults may cause significantly more serious consequences on the integrity and performance of the system. A possible solution is the use of a single error correcting-double error detecting (SEC/DED) code in the cache tag memory. However, the classical implementation of the SEC/DED code is proved to be inappropriate for the tag memory due to the required silicon area and time delays. In this paper we propose a new way of the SEC/DED code exploitation well-suited to cache tag memories. During fault free operation the proposed technique does not add any delay on the critical path of the cache, while in the case of a single error the delay is so small that the cache access time is increased by at most one CPU cycle. An example design shows the superiority of the proposed technique against the classical one. The application of the proposed scheme to real and virtual addressed caches of one or two levels is also discussed.

[1]  Hideto Hidaka,et al.  The cache DRAM architecture: a DRAM with an on-chip cache memory , 1990, IEEE Micro.

[2]  A. Jain,et al.  A CMOS VAX microprocessor with on-chip cache and memory management , 1987 .

[3]  Y. Ooi,et al.  Fault-tolerant architecture in a cache memory control LSI , 1992 .

[4]  B. R. Wilkins,et al.  Influences on soft error rates in static RAMs , 1987 .

[5]  R. E. Kessler,et al.  Inexpensive implementations of set-associativity , 1989, ISCA '89.

[6]  Kenji Maeguchi,et al.  A 32 kbyte integrated cache memory , 1989 .

[7]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[8]  Dhiraj K. Pradhan,et al.  Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems , 1987, IEEE Transactions on Computers.

[9]  Mark D. Hill,et al.  Performance Implications of Tolerating Cache Faults , 1993, IEEE Trans. Computers.

[10]  Robert W. Horst.  Reliable design of high-speed cache and control store memories , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[11]  Alan Jay Smith,et al.  Cache Memories , 1982, CSUR.

[12]  Steven A. Przybylski,et al.  Cache and memory hierarchy design: a performance-directed approach , 1990 .

[13]  Anant Agarwal,et al.  MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache , 1987 .

[14]  R. D. Freeman,et al.  CRISP: a pipelined 32-bit microprocessor with 13-kbit of cache memory , 1987 .

[15]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[16]  Norman P. Jouppi,et al.  Improving direct-mapped cache performance by the addition of a small fully-associative cache and pre , 1990, ISCA 1990.

[17]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[18]  R. L. Sites,et al.  ATUM: a new technique for capturing address traces using microcode , 1986, ISCA '86.

[19]  Gurindar S. Sohi.  Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors , 1989, IEEE Trans. Computers.

[20]  T. S. Liu.  The Role of a Maintenance Processor for a General-Purpose Computer System , 1984, IEEE Transactions on Computers.