论文信息 - On the propagation of faults and their detection in a hardware implementation of the Advanced Encryption Standard

On the propagation of faults and their detection in a hardware implementation of the Advanced Encryption Standard

High reliability is a desirable property of any implementation of the Advanced Encryption Standard (AES). To achieve high reliability, all possible faults must be detected to avoid the use and transmission of erroneous encrypted/decrypted data. In this paper we first study the behavior of faults which may occur during the encryption and decryption procedures of AES, and the way such faults eventually propagate to the final result. We then describe an appropriate detection technique for these faults. This work extends our preliminary results (G. Bertoni et al, MPCS 2002) by considering more general fault models (e.g., permanent and multiple transient faults), and the possibility of fault masking.

Israel Koren | Vincenzo Piuri | Guido Bertoni | Luca Breveglieri | Paolo Maistri

[1] Vincent Rijmen,et al. The Block Cipher Rijndael , 1998, CARDIS.

[2] Milos Drutarovský,et al. Two Methods of Rijndael Implementation in Reconfigurable Hardware , 2001, CHES.

[3] Ingrid Verbauwhede,et al. Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm , 2001, CHES.

[4] Vijay Kumar,et al. Efficient Rijndael Encryption Implementation with Composite Field Arithmetic , 2001, CHES.

[5] Máire O'Neill,et al. High Performance Single-Chip FPGA Rijndael Algorithm Implementations , 2001, CHES.

[6] Christophe Giraud,et al. An Implementation of DES and AES, Secure against Some Attacks , 2001, CHES.

[7] Bruce Schneier,et al. AES Key Agility Issues in High-Speed IPsec Implementations , 2000 .

[8] Ramesh Karri,et al. Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.