Evaluating Context Descriptions and Property Definition Patterns for Software Formal Validation

A well known challenge in the formal methods domain is to improve their integration with practical engineering methods. In the context of embedded systems, model checking requires first to model the system to be validated, then to formalize the properties to be satisfied, and finally to describe the behavior of the environment. This last point which we name as the proof context is often neglected. It could, however, be of great importance in order to reduce the complexity of the proof. The question is then how to formalize such a proof context. We experiment a language, named CDL (Context Description Language), for describing a system environment using actors and sequence diagrams, together with the properties to be checked. The properties are specified with textual patterns and attached to specific regions in the context. Our contribution is a report on several industrial embedded system applications.

[1]  Peter H. Feiler,et al.  The Architecture Analysis & Design Language (AADL): An Introduction , 2006 .

[2]  Jameleddine Hassine,et al.  Use Case Maps as a property specification language , 2007, Software & Systems Modeling.

[3]  B.H.C. Cheng,et al.  Real-time specification patterns , 2005, Proceedings. 27th International Conference on Software Engineering, 2005. ICSE 2005..

[4]  Jon Whittle Specifying Precise Use Cases with Use Case Charts , 2005, MoDELS Satellite Events.

[5]  Zohar Manna,et al.  The Temporal Logic of Reactive and Concurrent Systems , 1991, Springer New York.

[6]  Rajeev Alur,et al.  A Theory of Timed Automata , 1994, Theor. Comput. Sci..

[7]  Frédéric Boniol,et al.  Using context descriptions and property definition patterns for software formal verification , 2008, 2008 IEEE International Conference on Software Testing Verification and Validation Workshop.

[8]  Jean-Charles Roger,et al.  Exploitation de contextes et d'observateurs pour la validation formelle de modèles , 2006 .

[9]  Ketil Stølen,et al.  STAIRS towards formal design with sequence diagrams , 2005, Software & Systems Modeling.

[10]  George S. Avrunin,et al.  PROPEL: an approach supporting property elucidation , 2002, ICSE '02.

[11]  Radu Mateescu,et al.  Model Checking for Managers , 1999, SPIN.

[12]  George S. Avrunin,et al.  Patterns in property specifications for finite-state verification , 1999, Proceedings of the 1999 International Conference on Software Engineering (IEEE Cat. No.99CB37002).

[13]  Frédéric Boniol,et al.  Mise en œuvre de composants MDA pour la validation formelle de modèles de systèmes d'information embarqués , 2007, Ingénierie des Systèmes d Inf..

[14]  Nicolas Halbwachs,et al.  Synchronous Observers and the Verification of Reactive Systems , 1993, AMAST.

[15]  François Vernadat,et al.  Time Petri Nets Analysis with TINA , 2006, Third International Conference on the Quantitative Evaluation of Systems - (QEST'06).

[16]  Marius Bozga,et al.  IF-2.0: A Validation Environment for Component-Based Real-Time Systems , 2002, CAV.

[17]  Mamoun Filali,et al.  The Syntax and Semantics of FIACRE , 2009 .

[18]  Alain Kerbrat,et al.  CADP - A Protocol Validation and Verification Toolbox , 1996, CAV.

[19]  Itu-T Specification and Description Language (SDL) , 1999 .