Yield optimization of CMOS logic circuit designs

Unlike memory applications where a repetitive cell is used and a relative insensitivity to faults is obtained through redundancy, the optimization task of a designer for large logic chips is very complex. To date most of the design optimization for yield is done by minimizing the chip area and usage of preestablished design rules. Based on the existing framework of yield calculation (1–2), we have developed a program which computes the actual random photolithographic yield and allows the designer to interactively optimize his layout for yield.