Parameterizable VLSI architectures for the full-search block-matching algorithm

Systolic VLSI architectures for implementing the full-search block-matching algorithm are described. A large range of data rates can be efficiently covered by the proposed architectures. The input bandwidth problem for the search-area data is solved by on-chip line buffers, allowing a low frame-buffer access rate. An architecture for block-scan data input is described in detail. A VLSI realization with a low transistor count can be achieved by linear arrays in conjunction with compact memory blocks based on three-transistor cells. >