Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

This paper describes an accurate, yet analytical method to predict the key characteristics of a bang-bang controlled timing loop: namely, the jitter transfer (JTRAN), jitter generation (JG), and jitter tolerance (JTOL). The analysis basically derives a linearized model of the system, where the bang-bang phase detector is modeled as a set of two linearized gain elements and an additive white noise source. This phase detector (PD) model is by far the most extensive one in literature, which can correctly estimate the effects of random jitter, transition density, and finite loop latency on the loop characteristics. The described pseudo-linear analysis assumes the presence of random jitter at the PD input and the minimum jitter necessary to keep the linear model valid is derived, based on a describing function analysis and Nyquist stability analysis. The presented analysis re-confirms the findings of prior theories and provides theoretical basis to the prior empirically-drawn equations, such as those for the quantization noise power and the gain reduction in presence of a finite loop delay. The predictions based on the presented analysis match well with the results from time-accurate behavioral simulations.

[1]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[2]  Jaeha Kim,et al.  Fast and accurate event-driven simulation of mixed-signal systems with data supplementation , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[3]  R. Walker Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems , .

[4]  Salvatore Levantino,et al.  Noise Analysis and Minimization in Bang-Bang Digital PLLs , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Michael Peter Kennedy,et al.  Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  T. Toifl,et al.  0.94ps-rms-jitter 0.016mm/sup 2/ 2.5GHz multi-phase generator PLL with 360/spl deg/ digitally programmable phase shift for 10Gb/s serial links , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  Nicola Da Dalt,et al.  Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  P. Schvan,et al.  A fully integrated SiGe receiver IC for 10 Gb/s data rate , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[9]  John J. Paulos,et al.  An analysis of nonlinear behavior in delta-sigma modulators , 1987 .

[10]  Nicola Da Dalt A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

[11]  Jaeha Kim,et al.  Stochastic steady-state and AC analyses of mixed-signal systems , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[12]  Salvatore Levantino,et al.  Quantization Effects in All-Digital Phase-Locked Loops , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Deog-Kyoon Jeong,et al.  A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[14]  Leon M. Hall,et al.  Special Functions , 1998 .

[15]  Jaeha Kim,et al.  Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[16]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997, IEEE J. Solid State Circuits.

[17]  Deog-Kyoon Jeong,et al.  Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery , 2003 .

[18]  R. Mooney,et al.  An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[19]  Deog-Kyoon Jeong,et al.  Multi-gigabit-rate clock and data recovery based on blind oversampling , 2003, IEEE Commun. Mag..

[20]  Nicola Da Dalt,et al.  Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  Deog-Kyoon Jeong,et al.  A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..