Design of Low Power, Area Efficient 2–4 Mixed Logic Line Decoder

A unique idea based on mixed-logic design for line decoder is designed by connecting transmission gate logic, pass transistor dual-value logic and static CMOS. Conventional techniques use static CMOS circuit to implement the design. However the power dissipation is observed to be high and the primary reason behind rise in power is due to increase in number of transistors. Here the proposed design uses mixed logic technique and GDI logic to build decoder which significantly decreases the transistor's count that results in low power consumption. Compared with mixed logic the GDI gives better result in power consumption and also delay reduction. Both normal and an inverting decoder designs are implemented. The proposed decoder can operate at low supply voltage and it finds its space in low power applications. Experimental results reveal that the proposed circuits present a significant improvement in terms of power, delay and transistor count and it outperforms the conventional CMOS based design.