论文信息 - Architecture with 1x VCO - 字舞流文

Architecture with 1x VCO

I. A. Young | J. Barkatullah | Nasser A. Kurd | J. Griffin

[1] J.G. Maneatis,et al. Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2] B. Bhushan,et al. A 0.35 /spl mu/m CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.