Exploiting Crosstalk Effects in FPGAs for Generating True Random Numbers

This paper presents a new method for implementing TRNGs in FPGA devices, which relies on filling a region or the whole FPGA chip close to its maximal capacity and exploiting the interconnection network as intensely as possible. This way, there are strong chances for the design to exhibit a nondeterministic behavior. Our first design is a computationally intensive core that generates 64-bit numbers, accumulated into a fixed-point accumulator. The bits that exhibit the maximal entropy are then post-processed using the XOR-based bias reduction method. We prove that the resulting TRNG provides high quality random numbers. An explanation of the underlying phenomenon is proposed, based on electromagnetic interferences inside the chip and crosstalk effects. A systematic method for developing TRNG designs based on this approach is proposed and an improved TRNG architecture is then presented.

[1]  J. Gentle Random number generation and Monte Carlo methods , 1998 .

[2]  Sanyou Zeng,et al.  Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings , 2007, ICES.

[3]  Ingrid Verbauwhede,et al.  FPGA Vendor Agnostic True Random Number Generator , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[4]  Adrian Thompson,et al.  An Evolved Circuit, Intrinsic in Silicon, Entwined with Physics , 1996, ICES.

[5]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[6]  Pierre L'Ecuyer,et al.  TestU01: A C library for empirical testing of random number generators , 2006, TOMS.

[7]  Florent de Dinechin,et al.  When FPGAs are better at floating-point than microprocessors , 2008, FPGA '08.

[8]  Milos Drutarovský,et al.  True Random Number Generator Embedded in Reconfigurable Hardware , 2002, CHES.

[9]  M. Drutarovsky,et al.  A Robust Chaos-Based True Random Number Generator Embedded in Reconfigurable Switched-Capacitor Hardware , 2007, 2007 17th International Conference Radioelektronika.

[10]  Pavol Galajda,et al.  CHAOS-BASED TRUE RANDOM NUMBER GENERATOR EMBEDDED IN A MIXED-SIGNAL RECONFIGURABLE HARDWARE , 2006 .

[11]  Paul J. Layzell,et al.  Analysis of unconventional evolved electronics , 1999, CACM.

[12]  Kris Gaj,et al.  An embedded true random number generator for FPGAs , 2004, FPGA '04.

[13]  Christof Paar,et al.  Cryptographic Hardware and Embedded Systems - CHES 2002 , 2003, Lecture Notes in Computer Science.