Very fast Simulated Annealing for HW-SW partitioning

Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems and has been studied extensively in the past. With the wide av ailability of commercial platforms such as the Virtex-II Pro series from Xilinx that integrate p rocessors with reconfigurable logic, one major existing challenge is the lack of efficient algorithms that can generate very high-quality solutions by exploring a huge HW/SW exploration spacethe key criterion is to obtain such solutions at a speed suitable for integration into a compiler-based pa rtitioner. In this report, we make two contributions for HW-SW partitioning of applications spec ified as procedural call-graphs: 1) We prove that during partitioning, the execution time met ric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rat her than for all ancestors along paths to the root vertex. This enables move-based partitioning al gorithms such as Simulated Annealing (SA) to execute significantly faster, allowing call graphs w ith thousands of vertices to be processed in less than half a second 2) Additionally, we devise a new cost function for SA that ena bles searching of spaces overlooked by traditional SA cost functions for HW-SW partitioning, al lowing the discovery of additional partitioning solutions in a very efficient manner. We present experimental evidence on a very large design spac e with over 12000 problem instances. We generate the problem instances by varying the call-graph sizes from 20 to 1000 vertices, indegree/outdegree of vertices, communication-to-computati on ratios, and varying the area constraint on the hardware partition. Thousands of problem instances a r explored in a matter of minutes as compared to several hours or days using a traditional SA form ulation. Aggregate data collected