A optimized spur-reduction delta-sigma modulator for wideband frequency synthesizer

A spur-reduction technique is presented to achieve low fractional spurs for a 5-10 GHz frequency synthesizer. A wideband fractional-N frequency synthesizer is designed with digital multi-stage noise shaping (MASH) Delta-Sigma Modulator (DSM). The third-order MASH Structure (MASH 1-1-1) is optimized using FPGA for spur-reduction. It exhibits in-band fractional spur of -66.85dBc/Hz at 50 kHz offset and improved about 18dBc/Hz at 9 GHz. The theory of Fractional-N frequency synthesizers is also presented.

[1]  Chun-Huat Heng,et al.  A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO , 2003 .

[2]  Jaewook Shin,et al.  A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  T. Kamoto,et al.  High-speed multi-modulus prescaler IC , 1995, Proceedings of ICUPC '95 - 4th IEEE International Conference on Universal Personal Communications.

[4]  Jan Van der Spiegel,et al.  An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution , 1996 .

[5]  H. V. Sorensen,et al.  An overview of sigma-delta converters , 1996, IEEE Signal Process. Mag..

[6]  B. Miller,et al.  A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.

[7]  Bang-Sup Song,et al.  A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration , 2006, IEEE Journal of Solid-State Circuits.

[8]  Bar-Giora Goldberg.  Digital Techniques in Frequency Synthesis , 1995 .

[9]  Atsushi Iwata,et al.  A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping , 1987 .

[10]  Behzad Razavi,et al.  Challenges in the design of frequency synthesizers for wireless applications , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[11]  Bang-Sup Song,et al.  A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[12]  Mitchell D. Trott,et al.  A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis , 2002, IEEE J. Solid State Circuits.

[13]  Hugh Thompson,et al.  An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).