Performance evaluation of buffered multistage interconnection networks with look-ahead contention resolution scheme

Packet-switched multistage interconnection networks (MINs) have been widely used for parallel computer systems and digital data communication. It is well-known that the maximum throughput of an input-buffered switch is limited due to the head of line (HOL) blocking. To overcome the HOL blocking, a technique known as look-ahead contention resolution (LCR) is used. In this paper we first present an efficient model for the performance evaluation of MINs with the LCR scheme. Then we demonstrate by simulation that the proposed model offers an accurate and easy means for analyzing the LCR performance.