A Multi-encoding Approach for LTL Symbolic Satisfiability Checking

Formal behavioral specifications written early in the system-design process and communicated across all design phases have been shown to increase the efficiency, consistency, and quality of the system under development. To prevent introducing design or verification errors, it is crucial to test specifications for satisfiability. Our focus here is on specifications expressed in linear temporal logic (LTL). We introduce a novel encoding of symbolic transition-based Buchi automata and a novel, "sloppy," transition encoding, both of which result in improved scalability. We also define novel BDD variable orders based on tree decomposition of formula parse trees. We describe and extensively test a new multi-encoding approach utilizing these novel encoding techniques to create 30 encoding variations. We show that our novel encodings translate to significant, sometimes exponential, improvement over the current standard encoding for symbolic LTL satisfiability checking.

[1]  Rajeev Alur,et al.  A Temporal Logic of Nested Calls and Returns , 2004, TACAS.

[2]  Ulrike Sattler,et al.  BDD-Based Decision Procedures for K , 2002, CADE.

[3]  Robert P. Kurshan,et al.  An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment , 2005, CHARME.

[4]  Marco Roveri,et al.  Symbolic Implementation of Alternating Automata , 2006, CIAA.

[5]  Paul Gastin,et al.  Fast LTL to Büchi Automata Translation , 2001, CAV.

[6]  E. Riccobene,et al.  Automatic Review of Abstract State Machines by Meta Property Verification , 2010, NASA Formal Methods.

[7]  Jaco Geldenhuys,et al.  Larger Automata and Less Work for LTL Model Checking , 2006, SPIN.

[8]  C. Eisner,et al.  Efficient Detection of Vacuity in ACTL Formulaas , 1997, CAV.

[9]  Michael Fisher,et al.  A Normal Form for Temporal Logics and its Applications in Theorem-Proving and Execution , 1997, J. Log. Comput..

[10]  S. Anderson,et al.  Secure Synthesis of Code: A Process Improvement Experiment , 1999, World Congress on Formal Methods.

[11]  Andrei Voronkov,et al.  Automated Deduction—CADE-18 , 2002, Lecture Notes in Computer Science.

[12]  Denis Poitrenaud,et al.  SPOT: an extensible model checking library using transition-based generalized Bu/spl uml/chi automata , 2004, The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings..

[13]  Pierre Wolper,et al.  An Automata-Theoretic Approach to Automatic Program Verification (Preliminary Report) , 1986, LICS.

[14]  Fausto Giunchiglia,et al.  Improved Automata Generation for Linear Temporal Logic , 1999, CAV.

[15]  Marco Roveri,et al.  From PSL to NBA: a Modular Symbolic Encoding , 2006, 2006 Formal Methods in Computer Aided Design.

[16]  A. Prasad Sistla,et al.  The complexity of propositional linear temporal logics , 1982, STOC '82.

[17]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[18]  Adam Czubak,et al.  Minimal Büchi Automata for Certain Classes of LTL Formulas , 2009, 2009 Fourth International Conference on Dependability of Computer Systems.

[19]  Viktor Schuppan,et al.  Liveness Checking as Safety Checking , 2002, FMICS.

[20]  Dimitra Giannakopoulou,et al.  From States to Transitions: Improving Translation of LTL Formulae to Büchi Automata , 2002, FORTE.

[21]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[22]  Xavier Thirioux.  Simple and Efficient Translation from LTL Formulas to Buchi Automata , 2002, Electron. Notes Theor. Comput. Sci..

[23]  Moshe Y. Vardi.  Automata-Theoretic Model Checking Revisited , 2007, VMCAI.

[24]  Dana Fisman,et al.  A Framework for Inherent Vacuity , 2009, Haifa Verification Conference.

[25]  Frank Wolter,et al.  Monodic fragments of first-order temporal logics: 2000-2001 A.D , 2001, LPAR.

[26]  Jean-François Raskin,et al.  Antichains: Alternative Algorithms for LTL Satisfiability and Model-Checking , 2008, TACAS.

[27]  Zohar Manna,et al.  A Decision Algorithm for Full Propositional Temporal Logic , 1993, CAV.

[28]  Fabio Somenzi,et al.  Efficient Büchi Automata from LTL Formulae , 2000, CAV.

[29]  Luca Pulina,et al.  A self-adaptive multi-engine solver for quantified Boolean formulas , 2009, Constraints.

[30]  Jean-François Raskin,et al.  An Antichain Algorithm for LTL Realizability , 2009, CAV.

[32]  Stephan Merz,et al.  Emptiness of Linear Weak Alternating Automata , 2003 .

[33]  Edmund M. Clarke,et al.  Another Look at LTL Model Checking , 1994, Formal Methods Syst. Des..

[34]  E. Allen Emerson,et al.  Temporal and Modal Logic , 1991, Handbook of Theoretical Computer Science, Volume B: Formal Models and Sematics.

[35]  Kousha Etessami,et al.  Analysis of Recursive Game Graphs Using Data Flow Equations , 2004, VMCAI.

[36]  J. Van Leeuwen,et al.  Handbook of theoretical computer science - Part A: Algorithms and complexity; Part B: Formal models and semantics , 1990 .

[37]  Pierre Wolper,et al.  Simple on-the-fly automatic verification of linear temporal logic , 1995, PSTV.

[38]  Amir Pnueli,et al.  On the synthesis of a reactive module , 1989, POPL '89.

[39]  Marco Roveri,et al.  Syntactic Optimizations for PSL Verification , 2007, TACAS.

[40]  Roberto Sebastiani,et al.  "More Deterministic" vs. "Smaller" Büchi Automata for Efficient LTL Model Checking , 2003, CHARME.

[41]  Fred Kröger,et al.  Temporal Logic of Programs , 1987, EATCS Monographs on Theoretical Computer Science.

[42]  Moshe Y. Vardi.  Automata-Theoretic Model Checking Revisited , 2007, VMCAI.

[43]  Arie M. C. A. Koster,et al.  Treewidth: Computational Experiments , 2001, Electron. Notes Discret. Math..

[44]  Orna Kupferman,et al.  Vacuity Detection in Temporal Model Checking , 1999, CHARME.

[45]  Sofiène Tahar,et al.  Design for verification of SystemC transaction level models , 2005, Design, Automation and Test in Europe.

[46]  Pierre Wolper,et al.  Memory-efficient algorithms for the verification of temporal properties , 1990, Formal Methods Syst. Des..

[47]  George J. Milne,et al.  Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.

[48]  Klaus Schneider,et al.  Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy , 2001, LPAR.

[49]  Amir Pnueli,et al.  Automatic Hardware Synthesis from Specifications: A Case Study , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[50]  Moshe Y. Vardi,et al.  Treewidth in Verification: Local vs. Global , 2005, LPAR.

[51]  Moshe Y. Vardi,et al.  LTL Satisfiability Checking , 2007, SPIN.

[52]  Ilan Beer,et al.  Efficient Detection of Vacuity in Temporal Model Checking , 2001, Formal Methods Syst. Des..

[53]  Jean-Michel Couvreur,et al.  On-the-Fly Verification of Linear Temporal Logic , 1999, World Congress on Formal Methods.

[54]  Marco Roveri,et al.  Formal analysis of hardware requirements , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[55]  Andreas Podelski,et al.  ACSAR: Software Model Checking with Transfinite Refinement , 2007, SPIN.

[56]  Pierre Wolper,et al.  Reasoning About Infinite Computations , 1994, Inf. Comput..

[57]  Valentin Goranko,et al.  Tableau Tool for Testing Satisfiability in LTL: Implementation and Experimental Analysis , 2010, M4M.