Verify level control criteria for multi-level cell flash memories and their applications

In 1M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.

[1]  Tong Zhang,et al.  On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Young-Ho Lim,et al.  A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995 .

[3]  Shu Lin,et al.  Error control coding : fundamentals and applications , 1983 .

[4]  Yo-Hwan Koh,et al.  A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[5]  Sanghyuk Jung,et al.  Hierarchical architecture of flash-based storage systems for high performance and durability , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[6]  M. Darnell,et al.  Error Control Coding: Fundamentals and Applications , 1985 .

[7]  William H. Press,et al.  Numerical recipes , 1990 .

[8]  Guido Torelli,et al.  A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage , 2009, IEEE Journal of Solid-State Circuits.

[9]  Antony I. T. Rowstron,et al.  Migrating server storage to SSDs: analysis of tradeoffs , 2009, EuroSys '09.

[10]  Khanh Nguyen,et al.  A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[11]  Li-Pin Chang,et al.  Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs , 2008, 2008 Asia and South Pacific Design Automation Conference.

[12]  D. Kencke,et al.  A multilevel approach toward quadrupling the density of flash memory , 1998, IEEE Electron Device Letters.

[13]  Yukihide Kohira.  国際会議参加報告:Asia and South Pacific Design Automation Conference , 2012 .

[14]  Hyung-Kyu Lim,et al.  A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications , 1996, IEEE J. Solid State Circuits.

[15]  C. Boisrobert,et al.  Fiber Optic Communication Systems , 1979 .

[16]  Tong Zhang,et al.  Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory , 2010, 2010 IEEE Globecom Workshops.

[17]  Ken Takeuchi,et al.  A multipage cell architecture for high-speed programming multilevel NAND flash memories , 1998, IEEE J. Solid State Circuits.

[18]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[19]  Tanaka,et al.  A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories , 1997, Symposium 1997 on VLSI Circuits.

[20]  Anxiao Jiang,et al.  Error-correcting schemes with dynamic thresholds in nonvolatile memories , 2011, 2011 IEEE International Symposium on Information Theory Proceedings.

[21]  D. Ielmini,et al.  Electrical characterization of anomalous cells in phase change memory arrays , 2006, 2006 International Electron Devices Meeting.

[22]  P. Kalavade,et al.  Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling , 2004, IEEE Transactions on Device and Materials Reliability.

[23]  Sung-Soo Lee,et al.  A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology , 2011, 2011 IEEE International Solid-State Circuits Conference.

[24]  Sameh Elnikety,et al.  Migrating enterprise storage to SSDs: analysis of tradeoffs , 2008 .

[25]  Richard D. Wesel,et al.  Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization , 2011, 2011 IEEE Global Telecommunications Conference - GLOBECOM 2011.

[26]  K. Prall.  Scaling Non-Volatile Memory Below 30nm , 2007, 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop.

[27]  G. Servalli,et al.  A 45nm generation Phase Change Memory technology , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[28]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[29]  G. Agrawal.  Fiber‐Optic Communication Systems , 2021 .

[30]  Li-Pin Chang,et al.  A Hybrid Approach to NAND-Flash-Based Solid-State Disks , 2010, IEEE Transactions on Computers.

[31]  Robert K. Henderson,et al.  A 3×3, 5µm pitch, 3-transistor single photon avalanche diode array with integrated 11V bias generation in 90nm CMOS technology , 2010, 2010 International Electron Devices Meeting.

[32]  Jae-Duk Lee,et al.  Effects of floating-gate interference on NAND flash memory cell operation , 2002, IEEE Electron Device Letters.