VLSI Implementation of a Multi-Clock Data Transfer System

VLSI Implementation of a Multi-Clock Data Transfer System Shuo Li, Lihong Zhang, Memorial University of Newfoundland. Abstract: Data transfer systems normally include more than one clock, which may enhance the implementation difficulty due to non-synchronicity. This paper presents a full VLSI implementation of a two-clock data transfer system, including RTL design, physical design, and post-layout verification. Several electronic design automation tools, such as are used through this work including Cadence NC-VHDL, NC-Verilog, SOC Encounter, Synopsys Design Compiler (DC) and Prime Time (PT), are used. To meet the timing requirements, design iterations are performed by tuning synthesis constraints. The final layout design shows no setup time and hold time violations with a reasonable silicon area overhead in a 0.18um CMOS technology. The comparison of pre-layout and post-layout timing performances is also provided in the paper. Technical stream: Electronics, VLSI, and Microprocessors Format: Paper

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