Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

The increasing demand for highly miniaturized battery-powered ultralow cost systems (e.g., below 1 dollar) in emerging applications such as body, urban life and environment monitoring, and so on, has introduced many challenges in chip design. Such applications require high performance occasionally and very little energy consumption during most of the time to extend battery lifetime. In addition, they require real-time guarantees. Caches have been shown to be the most critical blocks in these systems due to their high energy/area consumption and hard-to-predict behavior. New, simple, hybrid-voltage operation (high Vcc and ultralow Vcc), single-Vcc domain L1 cache architectures based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with error detection and correction codes have been recently proposed. Such designs provide significant energy and area efficiency without jeopardizing reliability levels to still provide strong performance guarantees. In this brief, we analyze the efficiency of these designs during ultralow voltage operation. We identify the limits of such approaches by finding an energy-optimal voltage region through experimental models. The experimental results show that area efficiency is always achieved in the range 200-400 mV, whereas both energy and area gains occur above 250 mV, i.e., in near-threshold regime.

[1]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[2]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[3]  David Blaauw,et al.  CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[4]  Francisco J. Cazorla,et al.  The MPsim simulation tool , 2009 .

[5]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[6]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[7]  Reinhard Wilhelm,et al.  Fast and Efficient Cache Behavior Prediction , 1997 .

[8]  Yu Cao,et al.  Predictive Technology Model for Nano-CMOS Design Exploration , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[9]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[10]  Trevor Mudge,et al.  Yield-driven near-threshold SRAM design , 2007, ICCAD 2007.

[11]  David E. Culler,et al.  Lessons from a Sensor Network Expedition , 2004, EWSN.

[12]  Mateo Valero,et al.  ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches , 2012, GLSVLSI '12.

[13]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[14]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[15]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[16]  N. Muralimanohar,et al.  CACTI 6 . 0 : A Tool to Understand Large Caches , 2007 .

[17]  Saurabh Dighe,et al.  A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[18]  Francisco J. Cazorla,et al.  Hybrid high-performance low-power and ultra-low energy reliable caches , 2011, CF '11.

[19]  H. Fujiwara,et al.  An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment , 2007, 2007 IEEE Symposium on VLSI Circuits.

[20]  Mateo Valero,et al.  Efficient cache architectures for reliable hybrid voltage operation using EDC codes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  Reinhard Wilhelm,et al.  Efficient and Precise Cache Behavior Prediction for Real-Time Systems , 1999, Real-Time Systems.