Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InP HEMT technology
暂无分享,去创建一个
[1] Noboru Ishihara,et al. 3.5-Gb/s/spl times/4-ch Si bipolar LSI's for optical interconnections , 1995 .
[2] M. Yoneyama,et al. A super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-/spl mu/m GaAs MESFETs , 1996, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996.
[3] N. Ishihara,et al. A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique , 1994 .
[4] S. Nati,et al. A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution , 1997 .
[5] Hiroshi Ito,et al. 0.1-/spl mu/m InAlAs/InGaAs HEMTs with an InP-recess-etch stopper grown by MOCVD , 1995, Seventh International Conference on Indium Phosphide and Related Materials.