论文信息 - Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InP HEMT technology

Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 /spl mu/m gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2/sup 31/-1 PRBS data signal at 43 Gbit/s.

Kimikazu Sano | Eiichi Sano | Koichi Murata | T. Enoki | S. Sugitani

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