RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress

Improving accuracy in approximate real-time computing without violating thermal-energy constraints of the underlying hardware is a challenging problem. The execution of approximate real-time tasks can individually be bifurcated into two components: (i) execution of the mandatory part of the task to obtain a result of acceptable quality, followed by (ii) partial/complete execution of the optional part, which refines the initially obtained result, to increase the accuracy without violating the temporal-deadline. This paper introduces RePAiR, a novel task-allocation strategy for approximate real-time applications, combined with fine-grained DVFS and on-line task migration of the cores and power-gating of the last level cache, to reduce chip-temperature while respecting both deadline and thermal constraints. Furthermore, gained thermal benefits can be traded against system-level accuracy by extending the execution-time of the optional part.

[1]  Kevin Skadron,et al.  HotSpot 6.0: Validation, Acceleration and Extension , 2015 .

[2]  Ranjan Ghosh,et al.  Co-Scheduling Persistent Periodic and Dynamic Aperiodic Real-Time Tasks on Reconfigurable Platforms , 2018, IEEE Transactions on Multi-Scale Computing Systems.

[3]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[4]  Sparsh Mittal,et al.  A Survey of Techniques for Approximate Computing , 2016, ACM Comput. Surv..

[5]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[6]  Mingsong Chen,et al.  QoS-Adaptive Approximate Real-Time Computation for Mobility-Aware IoT Lifetime Optimization , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Hemangee K. Kapoor,et al.  Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design , 2019, ACM Trans. Design Autom. Electr. Syst..

[9]  Olivier Sentieys,et al.  Approximation-aware Task Deployment on Asymmetric Multicore Processors , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  Abhishek Roy,et al.  Energy-aware standby-sparing on heterogeneous multicore systems , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Fabrice Paillet,et al.  FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs , 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.