A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer

This paper presents a compact and power-efficient 3rd-order CT $\Delta\Sigma$ ADC with a single OTA. A 4-b fully-passive 2nd_ order noise-shaping SAR ADC is employed as the quantizer that inherently provides two additional noise shaping orders. Fabricated in 40nm CMOS, the prototype ADC consumes 1.16mW with a 500MHz clock rate. It achieves a Walden FoM of 17-fJ/conv.-step and occupies an area of only 0.029 mm2.