Algorithm for the choice of topology in reconfigurable on-chip networks with real-time support

Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures.

[1]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Efficient synthesis of networks on chip , 2003, Proceedings 21st International Conference on Computer Design.

[3]  Michael T. Goodrich,et al.  Algorithm design , 2001 .

[4]  Hoai Hoang,et al.  Switched real-time Ethernet in industrial applications - deadline partitioning , 2003, 9th Asia-Pacific Conference on Communications (IEEE Cat. No.03EX732).

[5]  Sharad Malik,et al.  A technology-aware and energy-oriented topology exploration for on-chip networks , 2005, Design, Automation and Test in Europe.

[6]  George N. Rouskas,et al.  A Survey of Virtual Topology Design Algorithms for Wavelength Routed Optical Networks , 1999 .

[7]  John P. Lehoczky,et al.  Integrated QoS-aware resource management and scheduling with multi-resource constraints , 2006, Real-Time Systems.

[8]  Fred Halsall,et al.  Data communications, computer networks and open systems (3. ed.) , 1995, Electronic-systems engineering series.

[9]  C. P. Ravikumar,et al.  Genetic algorithm for mapping tasks onto a reconfigurable parallel processor , 1995 .

[10]  Timothy Mark Pinkston,et al.  A methodology for designing efficient on-chip interconnects on well-behaved communication patterns , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[11]  George N. Rouskas,et al.  On the physical and logical topology design of large-scale optical networks , 2003 .

[12]  Luigi Fratta,et al.  Topological design of the wavelength-division optical network , 1990, Proceedings. IEEE INFOCOM '90: Ninth Annual Joint Conference of the IEEE Computer and Communications Societies@m_The Multiple Facets of Integration.

[13]  Radu Marculescu,et al.  Communication-centric SoC design for nanoscale domain , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[14]  Radu Marculescu,et al.  Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach , 2005, Design, Automation and Test in Europe.

[15]  Federico Angiolini,et al.  /spl times/pipes Lite: a synthesis oriented design library for networks on chips , 2005, Design, Automation and Test in Europe.

[16]  Mark A. Shayman,et al.  Single and multipath logical topology design and traffic grooming algorithm in IP over WDM networks , 2003, Proceedings. 12th International Conference on Computer Communications and Networks (IEEE Cat. No.03EX712).

[17]  L. Benini,et al.  Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[18]  Leonid Oliker,et al.  Analyzing Ultra-Scale Application Communication Requirements for a Reconfigurable Hybrid Interconnect , 2005, ACM/IEEE SC 2005 Conference (SC'05).

[19]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[20]  Hai Le Vu,et al.  A framework for solving logical topology design problems within constrained computation time , 2003, IEEE Communications Letters.

[21]  P. Borsook.  Data communications , 1994, IEEE Spectrum.

[22]  Luca Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[23]  Changdong Liu,et al.  Performance and testbed study of topology reconfiguration in IP over optical networks , 2002, IEEE Trans. Commun..

[24]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[25]  Luigi Carro,et al.  Energy and latency evaluation of NoC topologies , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[26]  José Duato,et al.  An algorithm for dynamic reconfiguration of a multicomputer network , 1991, Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing.

[27]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[28]  Michael T. Goodrich,et al.  Algorithm Design: Foundations, Analysis, and Internet Examples , 2001 .

[29]  Srinivasan Murali,et al.  Mapping and configuration methods for multi-use-case networks on chips , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[30]  Tapani Ahonen,et al.  Topology optimization for application-specific networks-on-chip , 2004, SLIP '04.

[31]  Andrew A. Chien,et al.  Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization , 2005, 2005 International Conference on Computer Design.

[32]  Giovanni De Micheli,et al.  Design, synthesis, and test of networks on chips , 2005, IEEE Design & Test of Computers.

[33]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[34]  Chung Laung Liu,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[35]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[36]  Luca Benini,et al.  Network-on-chip architectures and design methods , 2005 .

[37]  Lionel M. Ni,et al.  Network planning and tuning in switch-based LANs , 1998, Proceedings. 1998 International Conference on Parallel Processing (Cat. No.98EX205).

[38]  Kumar N. Sivarajan,et al.  Design of logical topologies: a linear formulation for wavelength-routed optical networks with no wavelength changers , 2001, TNET.

[39]  Sheng Wang,et al.  Dynamic routing and assignment of wavelength algorithms in multifiber wavelength division multiplexing networks , 2000, IEEE J. Sel. Areas Commun..

[40]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[41]  Luigi Carro,et al.  Design Space Exploration Comparing Homogeneous and Heterogeneous Network-on-Chip Architectures , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

[42]  Kumar N. Sivarajan,et al.  Design of Logical Topologies for Wavelength-Routed Optical Networks , 1996, IEEE J. Sel. Areas Commun..