Neural network implementation using a single MOST per synapse

A VLSI implementation of an artificial neural network using a single n-channel MOS (metal-oxide semiconductor) transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and by using a novel technique to manipulate negative weights. A simple multilayer perceptron (MLP) network was simulated using the SPICE circuit simulator and the performance of a hardware realization of the same MLP network was measured. Simulations and measurements are shown to agree well.