论文信息 - Optimal voltages and sizing for low power [CMOS VLSI]

Optimal voltages and sizing for low power [CMOS VLSI]

We provide analytical "back of the envelope" calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics.

Mircea R. Stan

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