Validation analysis and test flow optimization of VLSI chip

This paper gives a validation analysis on a high-performance general-purpose processor, using the 0.18 /spl mu/m process, and based on this analysis a test flow optimization algorithm is presented. The fault detection capacity of different test items is first analyzed. Then the validation information can be reused to generate a test item efficiency table. Based on this table, a tradeoff between test item efficiency and test time is achieved as the heuristic object for optimizing our test flow, which can save much test time of faulty chips. Compared to the dynamic programming algorithm, the complexity of our heuristic ordering algorithm has been decreased from O(dn2/sup n/) to O(dn/sup 3/). Several experimental results have shown that this algorithm is efficient.

[1]  Kwang-Ting Cheng,et al.  On structural vs. functional testing for delay faults , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[2]  Ronald S. Gyurcsik,et al.  Optimal ordering of analog integrated circuit tests to minimize test time , 1991, 28th ACM/IEEE Design Automation Conference.

[3]  Tsu-Shuan Chang,et al.  Scheduling for IC sort and test with preemptiveness via Lagrangian relaxation , 1995, IEEE Trans. Syst. Man Cybern..

[4]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  C. Mani Krishna,et al.  Optimal scheduling of signature analysis for VLSI testing , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[6]  Yann-Hang Lee,et al.  Optimal Scheduling of Signature Analysis for VLSI Testing , 1991, IEEE Trans. Computers.

[7]  Burnell G. West,et al.  Accuracy requirements in at-speed functional test , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).