Area-efficient Reed-Solomon decoder design for 10-100 Gb/s applications

With the extensive applications in high-speed communication systems, the current high-throughput Reed-Solomon decoders are required to achieve the target data rates from 10 Gb/s to 100 Gb/s with low hardware complexity. In this paper, pipeline interleaving inversionless Berlekamp-Massey (PI-iBM) algorithm and pipeline interleaving reformulated inversionless Berlekamp-Massey (PI-RiBM) algorithms for decoding Reed-Solomon codes are presented. Based on these two new algorithms PI-iBM and PI-RiBM Reed-Solomon decoders targeted at 10–100 Gb/s applications are developed. Compared with previously published works, the proposed designs can achieve very high throughput with relatively low hardware complexity. Thus they are well suited for modern high data rate communication systems.

[1]  Ming-Der Shieh,et al.  Design and implementation of efficient Reed-Solomon decoders for multi-mode applications , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[2]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[3]  Naresh R. Shanbhag,et al.  High-speed architectures for Reed-Solomon decoders , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Hanho Lee.  A high-speed low-complexity Reed-Solomon decoder for optical communications , 2005, IEEE Trans. Circuits Syst. II Express Briefs.

[5]  C. B. Shung,et al.  A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications , 1998 .

[6]  Hanho Lee.  High-speed VLSI architecture for parallel Reed-Solomon decoder , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  V. Kamakoti,et al.  Ultra folded high-speed architectures for Reed Solomon decoders , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[8]  Herbert O. Burton.  Inversionless decoding of binary BCH codes , 1971, IEEE Trans. Inf. Theory.

[9]  Shahid Rizwan,et al.  Retimed decomposed serial berlekamp-massey architecture for high-speed reed-solomon decoding = 고속 리드 솔로몬 디코딩을 위한 시간 조정되고 분해된 직렬 Berlekamp-Massey 구조 , 2005 .

[10]  Elwyn R. Berlekamp,et al.  Algebraic coding theory , 1984, McGraw-Hill series in systems science.

[11]  James L. Massey,et al.  Shift-register synthesis and BCH decoding , 1969, IEEE Trans. Inf. Theory.

[12]  X. Youzhi.  Implementation of Berlekamp-Massey algorithm without inversion , 1991 .

[13]  Trieu-Kien Truong,et al.  VLSI design of inverse-free Berlekamp-Massey algorithm , 1991 .

[14]  Toshio Horiguchi.  High‐speed decoding of BCH codes using a new error‐evaluation algorithm , 1989 .