Structure of double-port RAM for realizing flash memory controller cache and method for realizing same

A structure of a double-port RAM for realizing flash memory controller cache and a method for realizing same are disclosed; the structure comprises an IDE interface control logic, an IDE register, an IDE cache region, a processor, a Flash interface control logic, a FLASH cache region and an PPGA peripheral circuit; wherein the IDE register and the IDE cache region form an IDE interface cache region, and the IDE interface cache region and the FLASH cache region both comprises two completely independent control ports; the method for realizing the cache comprises random data reading out and writing in processes. The invention can realize random address reading and writing, and data reading and writing efficiencies are high.