A BIST approach for very deep sub-micron (VDSM) defects

This paper presents a BIST approach for the very deep submicron (VDSM) defects in an ASIC. As bridging or open defects are dominant in VDSM, efficient and accurate tests to detect them are now strongly required. We evaluated the BIST patterns for various criteria. These evaluations and additional real chip experiments have indicated that BIST has better detectability of defects than the conventional stored test.

[1]  Edward J. McCluskey,et al.  Analysis of pattern-dependent and timing-dependent failures in an experimental test chip , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  Yuyun Liao,et al.  Optimal voltage testing for physically-based faults , 1996, Proceedings of 14th VLSI Test Symposium.

[3]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[4]  Vishwani D. Agrawal,et al.  The path-status graph with application to delay fault simulation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[6]  Kazumi Hatayama,et al.  Low overhead test point insertion for scan-based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[7]  Anjali Kinra.  Towards reducing "functional only" fails for the UltraSPARC/sup TM/ microprocessors , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[8]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[9]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[11]  Siyad C. Ma,et al.  A comparison of bridging fault simulation methods , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[12]  Keith Baker,et al.  Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Edward J. McCluskey,et al.  Detecting delay flaws by very-low-voltage testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[14]  Hidekazu Terai,et al.  Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 , 1994, 31st Design Automation Conference.

[15]  Sreejit Chakravarty.  On the capability of delay tests to detect bridges and opens , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[16]  Wojciech Maly,et al.  Current signatures: application , 1997, Proceedings International Test Conference 1997.

[17]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[18]  Charles H. Stapper,et al.  Modeling of Defects in Integrated Circuit Photolithographic Patterns , 1984, IBM J. Res. Dev..