22FDX® fMAX Optimization through Parasitics Reduction and GM Boost

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The fMAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

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