Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology

This paper aims to provide reliability projections and modeling for wearout current consumption and oxide lifetime (or programming time) under programming conditions regarding OTP memories perimeter. TDDB reliability methodology have been carried out to high voltages and the power law dependent TBD equations terms have been discussed. Adjustments focusing on the temperature impact on voltage acceleration offer us a compact model for TDDB HV.

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