The design and implementation of a first-generation CELL processor - a multi-core SoC
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S. Asano | M. Suzuoki | D. Pham | M. Riley | H.P. Hofstee | M. Bolliger | M.N. Day | C. Johns | J. Kahle | A. Kameyama | J. Keaty | Y. Masubuchi | D. Shippy | D. Stasiak | J. Warnock | S. Weitzel | D. Wendel | K. Yazawa | M. Wang | T. Yamazaki
[1] S.H. Dhong,et al. A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..