Symbolic Boolean manipulation with ordered binary-decision diagrams
暂无分享,去创建一个
[1] C. Y. Lee. Representation of switching circuits by binary-decision programs , 1959 .
[2] F. F. Sellers,et al. Analyzing Errors with the Boolean Difference , 1968, IEEE Transactions on Computers.
[3] Eduard Cerny,et al. An Approach to Unified Methodology of Combinational Switching Circuits , 1977, IEEE Transactions on Computers.
[4] Erik Meineche Schmidt,et al. The Complexity of Equivalence and Containment for Free Single Variable Program Schemes , 1978, ICALP.
[5] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[6] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[7] Manuel Blum,et al. Equivalence of Free Boolean Graphs can be Decided Probabilistically in Polynomial Time , 1980, Inf. Process. Lett..
[8] Robert K. Brayton,et al. Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.
[9] Robert Hum,et al. Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing , 1984, ITC.
[10] Gerald J. Sussman,et al. Structure and interpretation of computer programs , 1985, Proceedings of the IEEE.
[11] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[12] A. P. Sistla,et al. Automatic verification of finite-state concurrent systems using temporal logic specifications , 1986, TOPL.
[13] Mary Jane Irwin,et al. Fast Methods for Switch-Level Verification of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Wolfram Büttner,et al. Embedding Boolean Expressions into Logic Programming , 1987, J. Symb. Comput..
[15] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[16] Ingo Wegener,et al. On the complexity of branching programs and decision trees for clique functions , 1988, JACM.
[17] Jean Christophe Madre,et al. Proving circuit correctness using formal comparison between expected and extracted behaviour , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[18] Randal E. Bryant,et al. Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation , 1989, 26th ACM/IEEE Design Automation Conference.
[19] C. L. Berman. Ordered binary decision diagrams and circuit structure , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[20] Christoph Meinel,et al. Modified Branching Programs and Their Computational Power , 1989, Lecture Notes in Computer Science.
[21] Allan L. Fisher,et al. Verifying pipelined hardware using symbolic logic simulation , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[22] Olivier Coudert,et al. Automating the diagnosis and the rectification of design errors with PRIAM , 1989, ICCAD 1989.
[23] Olivier Coudert,et al. Automating the diagnosis and the rectification of design errors with PRIAM , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[24] K. Karplus. Using if-then-else DAGs for multi-level logic minimization , 1989 .
[25] A. Richard Newton,et al. Don't care minimization of multi-level sequential logic networks , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[26] Olivier Coudert,et al. Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams , 1990, CAV.
[27] Robert K. Brayton,et al. Algorithms for discrete function manipulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[28] Edmund M. Clarke,et al. A parallel algorithm for constructing binary decision diagrams , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[29] Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.
[30] Jerry R. Burch,et al. Using bdds to verify multipliers , 1991, 28th ACM/IEEE Design Automation Conference.
[31] Olivier Coudert,et al. A Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver , 1991, IJCAI.
[32] Hiroyuki Ochi,et al. Breadth-first manipulation of SBDD of boolean functions for vector processing , 1991, 28th ACM/IEEE Design Automation Conference.
[33] Srinivas Devadas,et al. Boolean satisfiability and equivalence checking using general binary decision diagrams , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[34] Randal E. Bryant,et al. On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.
[35] Fabio Somenzi,et al. Variable ordering and selection of FSM traversal , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[36] Michael L. Bushnell,et al. EST: The new frontier in automatic test-pattern generation , 1990, DAC '90.
[37] Nagisa Ishiura,et al. Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits , 1991, 28th ACM/IEEE Design Automation Conference.
[38] Thomas Filkorn. A Method for Symbolic Verification of Synchronous Circuits , 1991 .
[39] Randal E. Bryant,et al. Formal hardware verification by symbolic ternary trajectory evaluation , 1991, 28th ACM/IEEE Design Automation Conference.
[40] Nagisa Ishiura,et al. Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.
[41] Masahiro Fujita,et al. Boolean resubstitution with permissible functions and binary decision diagrams , 1991, DAC '90.
[42] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[43] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[44] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[45] Kenneth L. McMillan,et al. Symbolic model checking: an approach to the state explosion problem , 1992 .
[46] Christoph Meinel,et al. Efficient Analysis and Manipulation of OBDDs can be Extended to Read-once-only Branching Programs , 1992, Universität Trier, Mathematik/Informatik, Forschungsbericht.
[47] Robert K. Brayton,et al. Heuristic minimization of multiple-valued relations , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..