Localization and characterization of latch‐up sensitive areas using a laser beam: Influence on design rules of ICs in CMOS technology

The technique of ‘scanning’ with a laser beam permits a localization of latch-up sites in CMOS technology with a resolution less than one micron. Electrical simulations correlated to experimental curves of ‘supply current’ versus ‘photo-induced current’ offer a good evaluation of the predominant parameters of the parasitic structure.