Hardware architecture dedicated for arithmetic mean filtration implemented in FPGA

An FPGA-based hardware architecture for arithmetic mean filtration optimized with 49-pixel square neighborhood is proposed. The arithmetic mean formula is optimized and transformed into the new formula that introduces the computational cyclic sequence which results in multiplication-less process with only 9 additions necessary for each pixel. The external memory is used to save partial results but the memory requirement has been optimized so the requirement is the same as for the input data. This proposed architecture is oriented to security tracking applications; however, it can be used in any image processing applications that use arithmetic mean filtering. It is resolution and frame rate independent and suitable for all high resolution and multiple camera systems. FPGA optimization made it also suitable for FPGA-based reconfigurable systems and computing.

[1]  Xudong Jiang,et al.  Iterative Truncated Arithmetic Mean Filter and Its Properties , 2012, IEEE Transactions on Image Processing.

[2]  Karianto Leman,et al.  Distributed system for multiple camera tracking , 2011, 2011 IEEE International Conference on Multimedia and Expo.

[3]  S. Chivapreecha,et al.  Distributed arithmetic LMS adaptive filter implementation without look-up table , 2012, 2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology.

[4]  M. C Hanumantharaju,et al.  A novel FPGA implementation of adaptive color image enhancement based on HSV color space , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[5]  Jung-Hyun Lee,et al.  Adaptive background generation for automatic detection of initial object region in multiple color-filter aperture camera-based surveillance system , 2012, 2012 IEEE International Conference on Consumer Electronics (ICCE).

[6]  Xudong Jiang,et al.  Further Properties and a Fast Realization of the Iterative Truncated Arithmetic Mean Filter , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Jianyu Yang,et al.  Adaptive Iterative Truncated Arithmetic Mean Filter in Image Denoising , 2012, 2012 IEEE 12th International Conference on Computer and Information Technology.

[8]  Aggelos K. Katsaggelos,et al.  Tracking-optimal pre- and post-processing for H.264 compression in traffic video surveillance applications , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[9]  Chu-Sing Yang,et al.  Adaptive camera assignment and hand-off algorithm in multiple active camera surveillance system , 2010, 2010 International Conference on Machine Learning and Cybernetics.

[10]  Yan Gao,et al.  Zoom control of wide area tracking system , 2010, 2010 5th IEEE International Conference Intelligent Systems.

[11]  Yi-Ping Hung,et al.  2D and 3D visualization with dual-resolution for surveillance , 2012, 2012 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops.

[12]  S. Mukhopadhyay.  Abstract spatial hybrid systems for image processing , 2003, 42nd IEEE International Conference on Decision and Control (IEEE Cat. No.03CH37475).

[13]  Yanhui Guo,et al.  Autonomous decentralized network security system , 2005, Proceedings. 2005 IEEE Networking, Sensing and Control, 2005..

[14]  Rafiahamed Shaik,et al.  FPGA implementation of Fast Block LMS adaptive filter using Distributed Arithmetic for high throughput , 2011, 2011 International Conference on Communications and Signal Processing.

[15]  Libor Preucil,et al.  FPGA based Speeded Up Robust Features , 2009, 2009 IEEE International Conference on Technologies for Practical Robot Applications.