A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC

Abstract In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is -227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is -131.2 dBc/Hz at offset of 100 MHz.

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