A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique

A 14-bit 250MS/s low power pipeline analog-to-digital converter (ADC) implemented in a 0.18μιη CMOS process is presented in this paper. A SHA-less 3.5-bit front-end is adopted to achieve low power design. An aperture error eliminating technique and flash ADC optimization design techniques such as capacitor splitting, interpolation, and offset calibration, are both used to achieve wideband input even for the front-end with resolution up to 3.5-bit. The post simulation results show this ADC achieves an SNR of 74.6 dB, an SNDR of 74.4 dB and an SFDR of 87.1 dB with a 70MHz input signal, while maintaining an SNR > 72.5 dB and an SFDR > 77.4 dB up to 900MHz input signals. The ADC consumes 120mW from a 1.8 V supply.

[1]  Bei Peng,et al.  A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[2]  Chao Wu,et al.  A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[3]  Byung-Moo Min,et al.  A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC , 2003, IEEE J. Solid State Circuits.

[4]  A.P. Chandrakasan,et al.  A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs , 2006, IEEE Journal of Solid-State Circuits.

[5]  S. Devarajan,et al.  A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC , 2009, IEEE Journal of Solid-State Circuits.

[6]  Maarten Vertregt,et al.  A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[7]  Zhihua Wang,et al.  A merged first and second stage for low power pipelined ADC , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[8]  Jonathan W. Valvano,et al.  A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC , 2008, IEEE Journal of Solid-State Circuits.

[9]  Xuqiang Zheng,et al.  A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.