SPIDER, A Chip Planner for ISL Technology

Chip planning refers to organizing the layout of a chip and determining the feasibility of integration of a design without performing a detailed layout. This paper describes a chip planning tool called SPIDER (Spatial Planning and Interactive Development Environment for Research), for planning the layout of custom VLSI chips specific to ISL (Integrated Schottky Logic) technology. The tool provides estimates for function block areas, interconnection wiring space and a floorplan. Novel features of the chip planner are described. These include, the idea of a sizing model and algorithms for dimension allocation.