DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework

In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a big impact on performance and contributes a significant part of the total consumed power. Conventional DDR3-based solutions are stretched thin as their maximum bandwidth is limited by the I/O count and interface speed. As new solutions are coming onto the market (JEDEC DDR4, JEDEC WIDE I/O, Micron’s hybrid memory cube: HMC or JEDEC’s high bandwidth memory: HBM) it is critical to evaluate the performance of these solutions and assess their suitability for specific applications. Furthermore, in systems with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. It is crucial to have a flexible and holistic DRAM subsystem framework for exhaustive design space explorations, which can handle all this different types of memories, as well as the aspects of performance, power and temperature.

[1]  T. Hamamoto,et al.  On the retention time distribution of dynamic random access memory (DRAM) , 1998 .

[2]  J. Thomas Pawlowski,et al.  Hybrid memory cube (HMC) , 2011, 2011 IEEE Hot Chips 23 Symposium (HCS).

[3]  Zhao Zhang,et al.  A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality , 2000, MICRO 33.

[4]  Thomas F. Wenisch,et al.  Simulating DRAM controllers for future system architecture exploration , 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[5]  Norbert Wehn,et al.  DRAM power management and energy consumption: a critical assessment , 2009, SBCCI.

[6]  Bruce Jacob,et al.  DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.

[7]  Seth H. Pugsley,et al.  USIMM : the Utah SImulated Memory Module , 2012 .

[8]  Onur Mutlu,et al.  Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems , 2008, 2008 International Symposium on Computer Architecture.

[9]  Wei-Fen Lin,et al.  Reducing DRAM latencies with an integrated memory hierarchy design , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[10]  Norbert Wehn,et al.  Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  David C. Black,et al.  SystemC: From the Ground Up, Second Edition , 2009 .

[12]  Luca Benini,et al.  Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[14]  David Atienza,et al.  3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[15]  Richard Veras,et al.  RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[16]  Tao Zhang,et al.  3D-SWIFT: a high-performance 3D-stacked wide IO DRAM , 2014, GLSVLSI '14.

[17]  Samuel Williams,et al.  Hardware/software co-design for energy-efficient seismic modeling , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[18]  William J. Dally,et al.  Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[19]  Norbert Wehn,et al.  DRAM selection and configuration for real-time mobile systems , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[20]  Luca Benini,et al.  Exploration and Optimization of 3-D Integrated DRAM Subsystems , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Norbert Wehn,et al.  TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration , 2013, RAPIDO '13.

[22]  Kevin Kai-Wei Chang,et al.  Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[23]  Kees G. W. Goossens,et al.  Improved Power Modeling of DDR SDRAMs , 2011, 2011 14th Euromicro Conference on Digital System Design.

[24]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[25]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[26]  Luca Benini,et al.  An energy efficient DRAM subsystem for 3D integrated SoCs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[27]  Norbert Wehn,et al.  A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers , 2014, ACM Trans. Embed. Comput. Syst..

[28]  Engin Ipek,et al.  PARDIS: a programmable memory controller for the DDRx interfacing standards , 2012, ISCA '12.

[29]  Luca Benini,et al.  Optimized active and power-down mode refresh control in 3D-DRAMs , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[30]  Frank Kesel.  Modellierung von digitalen Systemen mit SystemC: Von der RTL- zur Transaction-Level-Modellierung , 2012 .