Quick on-chip self- and mutual-inductance screen

In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 /spl mu/m technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previously published work. The 2/spl times/mutual inductance screening rule is presented and verified. The differences in on-chip inductance consideration, the significant frequency of a trapezoidal pulse, and the circuit modeling of on-chip inductance are also discussed.

[1]  Lawrence T. Pileggi,et al.  Performance computation for precharacterized CMOS gates with RC loads , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Gerard V. Kopcsay,et al.  High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..

[4]  E. Friedman,et al.  Figures of merit to characterize the importance of on-chip inductance , 1998, DAC.

[5]  A. Deutsch,et al.  The importance of inductance and inductive coupling for on-chip wiring , 1997, Electrical Performance of Electronic Packaging.

[6]  A. E. Ruehii.  Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .

[7]  Lawrence T. Pileggi,et al.  Generating sparse partial inductance matrices with guaranteed stability , 1995, ICCAD.

[8]  K.A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.

[9]  Paul Penfield,et al.  Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.

[10]  Mattan Kamon,et al.  FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .

[11]  Frederick Warren Grover,et al.  Inductance Calculations: Working Formulas and Tables , 1981 .

[12]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[13]  Lawrence N. Dworsky,et al.  Modern Transmission Line Theory and Applications , 1980 .

[14]  Shen Lin,et al.  Clocktree RLC extraction with efficient inductance modeling , 2000, DATE '00.

[15]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[16]  Albert E. Ruehli,et al.  Inductance calculations in a complex integrated circuit environment , 1972 .

[17]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  Byron L. Krauter,et al.  Generating sparse partial inductance matrices with guaranteed stability , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[19]  Lawrence T. Pileggi,et al.  SPIE: sparse partial inductance extraction , 1997, DAC.

[20]  O. Takahashi,et al.  A 1.0 GHz single-issue 64 b powerPC integer processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[21]  Lei He,et al.  An efficient inductance modeling for on-chip interconnects , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[22]  Lawrence Pileggi,et al.  Sparse Partial Inductance Extraction † , 1997 .

[23]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  J. Torres,et al.  Advanced copper interconnections for silicon CMOS technologies , 1995 .

[25]  E. E. Davidson,et al.  Long lossy lines (L/sup 3/) and their impact upon large chip performance , 1997 .

[26]  A. Ruehli,et al.  Three-dimensional inductance computations with partial element equivalent circuits , 1979 .

[27]  Dennis Sylvester,et al.  On-chip cross talk noise model for deep-submicrometer ULSI interconnect , 1998 .