A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture

Rapid progress on nanodevices points to a promising direction for future circuit design. However, since nanofabrication techniques are not yet mature, implementation of nanocircuits, at least on a large scale, in the near future is infeasible. To ease fabrication and overcome the problem of high defect levels in nanotechnology, hybrid nano/CMOS reconfigurable architectures are attractive choices. Moreover, if the current photolithography fabrication process can be used to manufacture the hybrid chips, the benefits of nanotechnologies can be realized today. Traditional reconfigurable architectures can only support partial or coarse-grain runtime reconfiguration due to their limited on-chip storage and long off-chip reconfiguration latency. Recent progress on nano Random Access Memories (RAMs), such as carbon nanotube-based RAM (NRAM), Phase-Change Memory (PCM), magnetoresistive RAM (MRAM), etc., provides us with a chance to realize on-chip fine-grain runtime reconfiguration. These nano RAMs have good compatibility with the current fabrication process. By utilizing them in the hybrid design, we can take advantage of both CMOS and nanotechnology, and greatly improve the logic density, resource utilization, and performance of our design. In this article, we propose a high-performance reconfigurable architecture, called NATURE, that utilizes CMOS logic and nano RAMs. An automatic design flow for NATURE is presented in Part II of the article. In NATURE, the highly dense nonvolatile nano RAMs are distributed throughout the chip to allow large embedded on-chip configuration storage, which enables fast reading and hence supports fine-grain runtime reconfiguration and temporal logic folding of a circuit before being mapped to the architecture. Temporal logic folding can significantly increase the logic density of NATURE (by over an order of magnitude for large circuits) while remaining competitive in performance and power consumption. For ease of exposition, we use NRAMs to illustrate various concepts in this article due to the excellent properties of NRAMs. However, other nano RAMs can also be used instead. Experimental results based on NRAMs establish the efficacy of NATURE.

[1]  P. Chow,et al.  The design of an SRAM-based field-programmable gate array. I. Architecture , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Jon M. Slaughter,et al.  Magnetoresistive random access memory using magnetic tunnel junctions , 2003, Proc. IEEE.

[3]  Shuichi Tahara,et al.  MRAM Applications Using Unlimited Write Endurance , 2007, IEICE Trans. Electron..

[4]  Charles M. Lieber,et al.  Carbon nanotube-based nonvolatile random access memory for molecular computing , 2000, Science.

[5]  Michael J. Wilson,et al.  Nanowire-based sublithographic programmable logic arrays , 2004, FPGA '04.

[6]  Mei Liu,et al.  Three-dimensional CMOL: three-dimensional integration of CMOS/nanomaterial hybrid digital circuits , 2007 .

[7]  D. Strukov,et al.  CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .

[8]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Hye-Jin Kim,et al.  A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

[11]  A. El Gamal,et al.  Architecture of field-programmable gate arrays , 1993, Proc. IEEE.

[12]  P. J. Burke An RF circuit model for carbon nanotubes , 2003 .

[13]  H. Meng,et al.  Spin torque transfer structure with new spin switching configurations , 2007 .

[14]  S. Lai,et al.  Current status of the phase change memory and its future , 2003, IEEE International Electron Devices Meeting 2003.

[15]  Majid Sarrafzadeh,et al.  Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs , 2004, J. Circuits Syst. Comput..

[16]  Russell Tessier,et al.  Balancing Logic Utilization and Area Efficiency in FPGAs , 2000, FPL.

[17]  Vaughn Betz,et al.  FPGA routing architecture: segmentation and buffering to optimize speed and density , 1999, FPGA '99.

[18]  G. Stix Nanotubes in the clean room. , 2005, Scientific American.

[19]  Steven M. Nowick,et al.  ACM Journal on Emerging Technologies in Computing Systems , 2010, TODE.

[20]  Charles M. Lieber,et al.  High Performance Silicon Nanowire Field Effect Transistors , 2003 .

[21]  Raphael Rubin,et al.  Design of FPGA interconnect for multilevel metallization , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[23]  Li Shang,et al.  Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.

[24]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[25]  James Kao,et al.  Subthreshold leakage modeling and reduction techniques , 2002, ICCAD 2002.

[26]  Li Shang,et al.  A Hybrid Nano/CMOS Dynamically Reconfigurable System , 2011 .

[27]  André DeHon,et al.  Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density , 1996 .

[28]  Hyungsoon Shin,et al.  Macro model and sense amplifier for a MRAM , 2002 .

[29]  Jing Guo,et al.  Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-κ Gate Dielectrics , 2004 .

[30]  R. Stanley Williams,et al.  CMOS-like logic in defective, nanoscale crossbars , 2004 .

[31]  Kinam Kim,et al.  Recent Advances in High Density Phase Change Memory (PRAM) , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[32]  R. Kiehl,et al.  Resonant tunneling transistor with quantum well base and high‐energy injection: A new negative differential resistance device , 1985 .

[33]  Wei Zhang,et al.  ALLCN: an automatic logic-to-layout tool for carbon nanotube based nanotechnology , 2005, 2005 International Conference on Computer Design.

[34]  R. Williams,et al.  Nano/CMOS architectures using a field-programmable nanowire interconnect , 2007 .

[35]  Wei Zhang,et al.  NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[36]  Raphael Rubin,et al.  3D Nanowire-Based Programmable Logic , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[37]  Vaughn Betz,et al.  How Much Logic Should Go in an FPGA Logic Block? , 1998, IEEE Des. Test Comput..

[38]  Jonathan Rose,et al.  The Design of an SRAM-Based Field-Programmable Gate Array — Part I : Architecture , 1999 .

[39]  Steven Trimberger,et al.  A time-multiplexed FPGA , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[40]  Wei Zhang,et al.  NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[41]  Tetsuhiro Suzuki,et al.  Toggle magnetic random access memory cells scalable to a capacity of over 100 megabits , 2008 .

[42]  R.F. Smith,et al.  Carbon Nanotube Based Memory Development and Testing , 2007, 2007 IEEE Aerospace Conference.

[43]  Bruce F. Cockburn,et al.  An electrical simulation model for the chalcogenide phase-change memory cell , 2003, Records of the 2003 International Workshop on Memory Technology, Design and Testing.

[44]  B. Gleixner,et al.  Evolution of phase change memory characteristics with operating cycles: Electrical characterization and physical modeling , 2007 .