BLOCK ALIGNMENT: A METHOD FOR INCREASING THE YIELD OF MEMORY CHIPS THAT ARE PARTIALLY GOOD
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[1] D. Morency,et al. 4Mb DRAM Circuit Features , 1987, ESSCIRC '87: 13th European Solid-State Circuits Conference.
[2] R. Glang. Measurement and Distribution of Faults on Defect Test Site Chips , 1989 .
[3] R.P. Cenker,et al. A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.
[4] C. Stapper. The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions , 1985 .
[5] R. Cenker,et al. A fault-tolerant 64K dynamic RAM , 1979, 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[6] Robert E. Busch,et al. A 4Mb DRAM with double-buffer static-column architecture , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[7] C.H. Stapper,et al. Integrated circuit yield statistics , 1983, Proceedings of the IEEE.
[8] C. H. Stapper,et al. Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..