A 2.4 GHz Low-Power Sixth-Order RF Bandpass $\Delta\Sigma$ Converter in CMOS

A sixth-order RF bandpass DeltaSigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.

[1]  J. Ryckaert,et al.  A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass ΣΔ ADC in 90nm CMOS , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[2]  S.P. Voinigescu,et al.  A Low-Noise 40-GS/s Continuous-Time Bandpass $\Delta\Sigma$ ADC Centered at 2 GHz for Direct Sampling Receivers , 2007, IEEE Journal of Solid-State Circuits.

[3]  W. Martin Snelgrove,et al.  On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion , 2000 .

[4]  Ut-Va Koc,et al.  Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications , 2004, ISCAS.

[5]  W. C. Black,et al.  Sub-sampling sigma-delta modulator for baseband processing , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[6]  SeongHwan Cho,et al.  A Time-Based Bandpass ADC Using , 2008 .

[7]  Philippe Bénabès,et al.  A parallel structure of a continuous-time filter for band-pass sigma-delta A/D converters , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[8]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[9]  SeongHwan Cho,et al.  A 1.5-GHz 63dB SNR 20mW direct RF sampling bandpass VCO-based ADC in 65nm CMOS , 2009, 2009 Symposium on VLSI Circuits.

[10]  Geert Van der Plas,et al.  A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[11]  E.J. van der Zwan,et al.  A 0.2 mW CMOS /spl Sigma//spl Delta/ modulator for speech coding with 80 dB dynamic range , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[12]  Bernard Mulgrew,et al.  On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  R. Schreier,et al.  Delta-sigma modulators employing continuous-time circuitry , 1996 .

[14]  Liesbet Van der Perre,et al.  A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass \Sigma \Delta ADC in 90nm CMOS , 2008 .

[15]  José Silva-Martínez,et al.  A 63 dB SNR, 75-mW Bandpass RF $\Sigma\Delta$ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-$\mu{\hbox {m}}$ SiGe BiCMOS Technology , 2007, IEEE Journal of Solid-State Circuits.