Diagnosis of clustered faults and wafer testing

A probabilistic diagnosis algorithm is presented for constant degree structures. The performance of the algorithm is analyzed under a negative binomial failure distribution to account for fault clustering. It is shown that the algorithm can correctly identify almost all units even when the yield is low (much lower than 50%) and when faults are clustered. A wafer test structure is proposed, which utilizes the test access port of each die to perform comparison tests on its neighbors and incorporates a localized version of the diagnosis algorithm to determine the status of each die. Both the test time and the diagnosis time are invariant with respect to the number of dies on the wafer. The saving of test costs could be significant as compared with probe testing, because with probe testing dies are probed one at a time while they are tested in parallel with this scheme. The scheme is unique in that it is shown to work well when faults are clustered and when the yield is low.

[1]  Kyung-Yong Chwa,et al.  Schemes for Fault-Tolerant Computing: A Comparison of Modularly Redundant and t-Diagnosable Systems , 1981, Inf. Control..

[2]  Israel Koren,et al.  Yield Models for Defect-Tolerant VLSI Circuits: A Review , 1989 .

[3]  Sampath Rangarajan,et al.  Probabilistic diagnosis of multiprocessor systems with arbitrary connectivity , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[4]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[5]  Edward R. Scheinerman.  Almost Sure Fault Tolerance in Random Graphs , 1987, SIAM J. Comput..

[6]  GERNOT METZE,et al.  On the Connection Assignment Problem of Diagnosable Systems , 1967, IEEE Trans. Electron. Comput..

[7]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[8]  Kaiyuan Huang.  System Level Diagnosis and Wafer Testing , 1992 .

[9]  Vinod K. Agarwal,et al.  A Generalized Theory for System Level Diagnosis , 1987, IEEE Transactions on Computers.

[10]  Arnold O. Allen,et al.  Probability, statistics and queueing theory - with computer science applications (2. ed.) , 1981, Int. CMG Conference.

[11]  Krishan K. Sabnani,et al.  The Comparison Approach to Multiprocessor Fault Diagnosis , 1987, IEEE Transactions on Computers.

[12]  Vinod K. Agarwal,et al.  A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing , 1995, IEEE Trans. Parallel Distributed Syst..

[13]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[14]  S. Louis Hakimi,et al.  Characterization of Connection Assignment of Diagnosable Systems , 1974, IEEE Transactions on Computers.

[15]  Israel Koren,et al.  A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits , 1993, IEEE Trans. Computers.

[16]  Sampath Rangarajan,et al.  Probabilistic diagnosis algorithms tailored to system topology , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[17]  B. Nadeau-Dostie,et al.  A scan-based BIST technique using pair-wise compare of identical components , 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

[18]  Sampath Rangarajan,et al.  Built-In Testing of Integrated Circuit Wafers , 1990, IEEE Trans. Computers.

[19]  Douglas M. Blough,et al.  Fault detection and diagnosis in multiprocessor systems , 1988 .

[20]  Fabrizio Grandoni,et al.  A Theory of Diagnosability of Digital Systems , 1976, IEEE Transactions on Computers.

[21]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Prathima Agrawal,et al.  Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks , 1975, IEEE Transactions on Computers.

[23]  Gerald M. Masson,et al.  An 0(n2.5) Fault Identification Algorithm for Diagnosable Systems , 1984, IEEE Transactions on Computers.